gmacgrp_mac_address116_high
<b> Register 711 (MAC Address116 High Register)</b>
The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address116 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address116 Low Register must be performed after at least four clock cycles in the destination clock domain.
Module Instance | Base Address | Register Address |
---|---|---|
i_emac_emac0 | 0xFF800000 | 0xFF800B20 |
i_emac_emac1 | 0xFF802000 | 0xFF802B20 |
i_emac_emac2 | 0xFF804000 | 0xFF804B20 |
Size: 32
Offset: 0xB20
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ae RW 0x0 |
reserved_30_16 RO 0x0 |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
addrhi RW 0xFFFF |
gmacgrp_mac_address116_high Fields
Bit | Name | Description | Access | Reset | ||||||
---|---|---|---|---|---|---|---|---|---|---|
31 | ae |
Address Enable When this bit is set, the address filter module uses the 117th MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
|
RW | 0x0 | ||||||
30:16 | reserved_30_16 |
Reserved |
RO | 0x0 | ||||||
15:0 | addrhi |
MAC Address116 [47:32] This field contains the upper 16 bits (47:32) of the 117th 6-byte MAC address. |
RW | 0xFFFF |