dmagrp_transmit_poll_demand

         <b> Register 1 (Transmit Poll Demand Register) </b>

The Transmit Poll Demand register enables the Tx DMA to check whether or not the DMA owns the current descriptor. The Transmit Poll Demand command is given to wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the Suspend mode because of an Underflow error in a transmitted frame or the unavailability of descriptors owned by it. You can give this command anytime and the Tx DMA resets this command when it again starts fetching the current descriptor from host memory. When this register is read, it always returns zero.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF801004`
`i_emac_emac1`	`0xFF802000`	`0xFF803004`
`i_emac_emac2`	`0xFF804000`	`0xFF805004`

Size: 32

Offset: 0x1004

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`tpd` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`tpd` `RW 0x0`

dmagrp_transmit_poll_demand Fields

Bit	Name	Description	Access	Reset
31:0	`tpd`	Transmit Poll Demand When these bits are written with any value, the DMA reads the current descriptor pointed to by Register 18 (Current Host Transmit Descriptor Register). If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

tpd

Transmit Poll Demand

When these bits are written with any value, the DMA reads the current descriptor pointed to by Register 18 (Current Host Transmit Descriptor Register). If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes.

RW

0x0