gmacgrp_timestamp_control

         <b> Register 448 (Timestamp Control Register) </b>

This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.

Note: 
 * Bits[5:1] are reserved when External Timestamp Input feature is enabled. 
 * Bits[19:8] are reserved and read-only when Advanced Timestamp feature is not enabled.
 * Bits[28:24] are reserved and read-only when Auxiliary Snapshot feature is not enabled.
 * Release 3.60a onwards, the functions of Bits 17 and 16 (SNAPTYPSEL) have changed. These functions are not backward compatible with the functions described in release 3.50a.

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF800700`
`i_emac_emac1`	`0xFF802000`	`0xFF802700`
`i_emac_emac2`	`0xFF804000`	`0xFF804700`

Size: 32

Offset: 0x700

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`reserved_31_29` `RO 0x0`			`atsen3` `RO 0x0`	`atsen2` `RO 0x0`	`atsen1` `RO 0x0`	`atsen0` `RO 0x0`	`atsfc` `RO 0x0`	`reserved_23_19` `RO 0x0`					`tsenmacaddr` `RW 0x0`	`snaptypsel` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`tsmstrena` `RW 0x0`	`tsevntena` `RW 0x0`	`tsipv4ena` `RW 0x1`	`tsipv6ena` `RW 0x0`	`tsipena` `RW 0x0`	`tsver2ena` `RW 0x0`	`tsctrlssr` `RW 0x0`	`tsenall` `RW 0x0`	`reserved_7_6` `RO 0x0`		`tsaddreg` `RO 0x0`	`tstrig` `RO 0x0`	`tsupdt` `RO 0x0`	`tsinit` `RO 0x0`	`tscfupdt` `RO 0x0`	`tsena` `RW 0x0`

gmacgrp_timestamp_control Fields

Bit

Name

Description

Access

Reset

31:29

reserved_31_29

Reserved

RO

0x0

atsen3

Auxiliary Snapshot 3 Enable

This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. 

This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is not selected during core configuration or the selected number in the <i>Number of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than four.

RO

0x0

atsen2

Auxiliary Snapshot 2 Enable

This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. 

This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is not selected during core configuration or the selected number in the <i>Number of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than three.

RO

0x0

atsen1

Auxiliary Snapshot 1 Enable

This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. 

This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is not selected during core configuration or the selected number in the <i>Number of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than two.

RO

0x0

atsen0

Auxiliary Snapshot 0 Enable

This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. 

This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is not selected during core configuration.

Value	Description
0x0	DISABLED
0x1	ENABLED

RO

0x0

atsfc

Auxiliary Snapshot FIFO Clear

When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration.

Value	Description
0x0	DISABLED
0x1	ENABLED

RO

0x0

23:19

reserved_23_19

Reserved

RO

0x0

tsenmacaddr

Enable MAC address for PTP Frame Filtering

When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

17:16

snaptypsel

Select PTP packets for Taking Snapshots

These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken.

RW

0x0

tsmstrena

Enable Snapshot for Messages Relevant to Master

When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node.

Value	Description
0x0	SLAVE
0x1	MASTER

RW

0x0

tsevntena

Enable Timestamp Snapshot for Event Messages 

When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

tsipv4ena

Enable Processing of PTP Frames Sent over IPv4-UDP

When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default.

Value	Description
0x0	NO_PROCESS_PTP
0x1	PROCESS_PTP

RW

0x1

tsipv6ena

Enable Processing of PTP Frames Sent Over IPv6-UDP 

When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets.

Value	Description
0x0	NO_PROCESS_PTP
0x1	PROCESS_PTP

RW

0x0

tsipena

Enable Processing of PTP over Ethernet Frames

When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets.

Value	Description
0x0	NO_PROCESS_PTP
0x1	PROCESS_PTP

RW

0x0

tsver2ena

Enable PTP packet Processing for Version 2 Format

When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format.

Value	Description
0x0	PTP_1588_VER1
0x1	PTP_1588_VER2

RW

0x0

tsctrlssr

Timestamp Digital or Binary Rollover Control

When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit.

Value	Description
0x0	NOTIMESTAMP_LOW_ROLL_MAX
0x1	TIMESTAMP_LOW_ROLL_1NS

RW

0x0

tsenall

Enable Timestamp for All Frames

When set, the timestamp snapshot is enabled for all frames received by the MAC.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

7:6

reserved_7_6

Reserved

RO

0x0

tsaddreg

Addend Reg Update

When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it.

Value	Description
0x0	NOTIMESTAMP_ADDEND_UPDATED
0x1	TIMESTAMP_ADDEND_UPDATED

RO

0x0

tstrig

Timestamp Interrupt Trigger Enable

When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt.

Value	Description
0x0	NOTIMESTAMP_INTR_TRIG_EN
0x1	TIMESTAMP_INTR_TRIG_EN

RO

0x0

tsupdt

Timestamp Update

When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). 

This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The Timestamp Higher Word register (if enabled during core configuration) is not updated.

Value	Description
0x0	NOTIMESTAMP_UPDATED
0x1	TIMESTAMP_UPDATED

RO

0x0

tsinit

Timestamp Initialize

When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register).

This bit should be read zero before updating it. This bit is reset when the initialization is complete. The Timestamp Higher Word register (if enabled during core configuration) can only be initialized.

Value	Description
0x0	NOTIMESTAMP_INIT
0x1	TIMESTAMP_INIT

RO

0x0

tscfupdt

Timestamp Fine or Coarse Update

When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method.

Value	Description
0x0	TIMESTAMP_COARSE
0x1	TIMESTAMP_FINE

RO

0x0

tsena

Timestamp Enable

When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode.
On the receive side, the MAC processes the 1588 frames only if this bit is set.

Value	Description
0x0	NOTIMESTAMP
0x1	TIMESTAMP

RW

0x0