dmagrp_operation_mode

Reserved

Disable Dropping of TCP/IP Checksum Error Frames

When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset.

If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0).

Receive Store and Forward

When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits.

Disable Flushing of Received Frames

When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. 

This bit is reserved (and RO) in the GMAC-MTL configuration.

MSB of Threshold for Activating Flow Control 

If the DWC_gmac is configured for an Rx FIFO depth of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFA (Bits[10:9]) gives the following thresholds for activating flow control:

 * 100: Full minus 5 KB, that is, FULL - 5KB
 * 101: Full minus 6 KB, that is, FULL - 6KB
 * 110: Full minus 7 KB, that is, FULL - 7KB
 * 111: Reserved
 
This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.

MSB of Threshold for Deactivating Flow Control 

If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits[12:11]) gives the following thresholds for deactivating flow control:

 * 100: Full minus 5 KB, that is, FULL - 5KB
 * 101: Full minus 6 KB, that is, FULL - 6KB
 * 110: Full minus 7 KB, that is, FULL - 7KB
 * 111: Reserved 
 
This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.

Transmit Store and Forward

When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are ignored. This bit should be changed only when the transmission is stopped.

Flush Transmit FIFO

When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is completed. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. 

Note: The flush operation is complete only when the Tx FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. To complete this flush operation, the PHY transmit clock (clk_tx_i) is required to be active.

Reserved

Transmit Threshold Control

These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. 
 * 000: 64
 * 001: 128
 * 010: 192
 * 011: 256
 * 100: 40
 * 101: 32
 * 110: 24
 * 111: 16

Start or Stop Transmission Command

When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. 

When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state.

Threshold for Deactivating Flow Control (in half-duplex and full-duplex)

These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. 

 - 00: Full minus 1 KB, that is, FULL - 1KB
 - 01: Full minus 2 KB, that is, FULL - 2KB
 - 10: Full minus 3 KB, that is, FULL - 3KB
 - 11: Full minus 4 KB, that is, FULL - 4KB

The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB.
Note: For proper flow control, the value programmed in the "RFD_2, RFD" fields should be equal to or more than the value programmed in the "RFA_2, RFA" fields.

Threshold for Activating Flow Control (in half-duplex and full-duplex)

These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated.

 - 00: Full minus 1 KB, that is, FULL - 1KB
 - 01: Full minus 2 KB, that is, FULL - 2KB
 - 10: Full minus 3 KB, that is, FULL - 3KB
 - 11: Full minus 4 KB, that is, FULL - 4KB

These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB.

Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition.

Reserved

Forward Error Frames

When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped.
In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus.
When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is
written, then a partial frame may be forwarded to the DMA.

Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status in the following configurations:
 * The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected.
 * The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features:
- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations
- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations.

Forward Undersized Good Frames

When set, the Rx FIFO forwards Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC.

When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01.

Drop Giant Frames
When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO.

Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default:
 * Configurations in which IP Checksum Offload (Type 1) is selected in Rx
 * Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format
 * Configurations in which the Advanced Timestamp feature is selected
In all other configurations, this bit is not used (reserved and always reset).

Receive Threshold Control

These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are transferred automatically. 

The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.
 * 00: 64
 * 01: 32
 * 10: 96
 * 11: 128

Operate on Second Frame

When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.

Start or Stop Receive

When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. 

When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state.

Reserved