External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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8.3. LPDDR5 Layout Design Guidelines

This section provides PCB layout design recommendations and guidelines for Agilex™ 5 E-Series Group B FPGA devices with GPIO-B (Input/Output) silicon implementation.

A successful DDR design on PCB requires not only following the topology and routing guidelines provided here, but also must meet PDN design requirements. For power delivery network (PDN) design guideline information, refer to Agilex™ 5 Power Distribution Network Design Guidelines, available on the Intel website. For high-speed transceiver PCB layout guidelines, refer to Agilex™ 5 High Speed PCB Layout Design Guidelines, availabel on the Intel website.