External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
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4.3.6. s0_axi4 for EMIF

Fabric AXI interface to controller.

Table 47.  Interface: s0_axi4Interface type: axi4
Port Name Direction Description
Write Address (Command) Channel
s0_axi4_awaddr input Write address
s0_axi4_awburst input Write burst type.
  • ’b00 = Reserved (FIXED is not supported).
  • ’b01 = INCR.
  • ’b10 = WRAP.
  • ’b11 = Reserved.
s0_axi4_awid input Write address ID
s0_axi4_awlen input Write burst length. Any value between 0 and 255 is valid, representing a transfer of 1 to 256 beats.
s0_axi4_awlock input Write lock type. This 2-bit signal is used to control exclusive accesses and locking.
  • ’b0 = Normal Access.
  • ’b1 = Exclusive Access.
s0_axi4_awqos input Write quality of service. Supported priority values range from 0 to 3, with 0 as the lowest priority.
s0_axi4_awsize input Write burst size. AWSIZE = 5 (32 bytes) is supported by the memory controller when the AXI port is 256 bits, and only AWSIZE = 4 (16 bytes) is supported by the memory controller when the AXI port is 128 bits.
s0_axi4_awvalid input Write address valid
s0_axi4_awuser input Write address user signal.
  • [0]: Enable/Disable Auto-precharge.Drive 1 to enable Auto-precharge.An auto-precharge will be issued after the write command is completed.
  • [1]: ALLSTRB: When all write strobes are driven (no byte enable signals not asserted), this signal can be enabled to improve controller performance.
  • [13:2]: Not connected. Drive 0.
s0_axi4_awprot input Write protection type. This 2-bit signal is used to control privileged and secure accesses.
  • ’b00 = Non-Privileged & Secure Access.
  • ’b01 = Privileged & Secure Access.
  • ’b10 = Non-Privileged & Non-Secure.
  • ’b11 = Privileged & Non-Secure.
s0_axi4_awready output Write address ready
Write Data Channel
s0_axi4_wdata input Write data
s0_axi4_wlast input Write last. This signal indicates the last transfer in a write burst.
s0_axi4_wready output Write ready. Indicates that the AXI port is ready to accept write data.
s0_axi4_wstrb input Write strobes
s0_axi4_wuser input Write user signal. Only applicable to the x40/x72 lockstep cases. The additional user bits to be written are sent on this interface. If a x36 interface is used, then only the lowest 32-bits are connected.
s0_axi4_wvalid input Write valid
Write Response Channel
s0_axi4_bready input Response ready
s0_axi4_bid output Write response ID
s0_axi4_bresp output Write response. A response is sent for the entire burst.
  • ’b00 = OKAY. Write command was successfully processed, or exclusive write command was not processed as exclusive.
  • ’b01 = EXOKAY. Exclusive write command was successfully processed.
  • ’b10 = SLVERR. Slave has received the read write command but there is an error in the transaction.
  • ’b11 = DECERR. Slave does not exist and/or there is an error with the transaction.
s0_axi4_bvalid output Write response valid.
Read Address (Command) Channel
s0_axi4_araddr input Read address.
s0_axi4_arburst input Read burst type.
  • ’b00 = Reserved (FIXED is not supported).
  • ’b01 = INCR.
  • ’b10 = WRAP.
  • ’b11 = Reserved.
s0_axi4_arid input Read write address ID
s0_axi4_arlen input Read burst length. Any value between 0 and 128 255 is valid, representing a transfer of 1 to 256 beats.
s0_axi4_arlock input Read lock type. This 2-bit signal is used to control exclusive accesses and locking.
  • ’b0 = Normal Access.
  • ’b1 = Exclusive Access.
s0_axi4_arqos input Read quality of service Supported priority values range from 0 to 3, with 0 as the lowest priority
s0_axi4_arsize input Read burst size. AWSIZE = 5 (32 bytes) is supported by the memory controller when the AXI port is 256 bits, and only AWSIZE = 4 (16 bytes) is supported by the memory controller when the AXI port is 128 bits.
s0_axi4_arvalid input Read address valid.
s0_axi4_aruser inout Read address user signal.
  • [0]: Enable/Disable Auto-precharge. Drive 1 to enable auto-precharge.An auto-precharge will be issued after the read command is completed.
  • [13:1]: Not connected.Drive 0.
s0_axi4_arprot input Read protection type. This 2-bit signal is used to control privileged ad secure accesses.
  • ’b00 = Non-Privileged & Secure Access.
  • ’b01 = Privileged & Secure Access.
  • ’b10 = Non-Privileged & Non-Secure.
  • ’b11 = Privileged & Non-Secure.
s0_axi4_arready output Read address ready
Ready Data Channel
s0_axi4_rdata output Read data
s0_axi4_rid output Read ID
s0_axi4_rlast output Read last. This signal indicates the last transfer in a read burst.
s0_axi4_rready input Read ready
s0_axi4_rresp output read response. A response is sent with each burst, indicating the status of that burst.
  • ’b00 = OKAY. Read command was successfully processed, or exclusive read command was not processed as exclusive.
  • ’b01 = EXOKAY. Exclusive read command was successfully processed.
  • ’b10 = SLVERR. Slave has received the read command but there is an error in the transaction.
  • ’b11 = DECERR. Slave does not exist and/or there is an error with the transaction.
s0_axi4_ruser output Read user signal. Only applicable to the x40/x72 lockstep cases. These are the additional user bits received on this interface. If a x36 interface is used, then only the lowest 32-bits are connected.
s0_axi4_rvalid output Read valid.