External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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Document Table of Contents

6.2.3.3. General Guidelines

Observe the following general guidelines when placing pins for your Intel® Agilex™ 5 external memory interface.

  1. Ensure that the pins of a single external memory interface reside on the same edge I/O.
  2. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the table in the Address and Command Pin Placement for DDR4 topic.
  3. Not every byte lane can function as an address and command lane or a data lane. The pin assignment must adhere to the DDR4 data width mapping defined in the DDR4 Data Width Mapping topic.
  4. A byte lane must not be used by both address and command pins and data pins.
  5. An HSIO bank cannot be used for more than one interface – meaning that two sub-banks belonging to two different EMIF interfaces are not permitted.
  6. You may not share byte lanes within a sub-bank for two different interfaces; you can assign byte lanes within a sub-bank to one EMIF interface only.
  7. Any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin:
    • For fabric EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same sub-bank, pins in an I/O lane that is not assigned to an EMIF interface, can be used as general purpose I/O pins.
    • For HPS EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same bank, pins in an I/O lane that is not assigned to an EMIF interface cannot be used as general purpose I/O pins either.
  8. All address and command pins and their associated clock pins (CK_t and CK_c) must reside within a single sub-bank. Refer to the table in the DDR4 Data Width Mapping topic for the supported address and command and data lane placements.
  9. One of the sub-banks in the device (typically the sub-bank within corner bank 3A) may not be available if you use certain device configuration schemes. For some schemes, there may be an I/O lane available for EMIF data group.
    • AVST-8 – This is contained entirely within the SDM, therefore all lanes of sub-bank 3A can be used by the external memory interface.
    • AVST-16 – Byte lanes 6 contains SDM_DATA[25:16], and is not used by AVSTx16.However, the external memory interface cannot use byte lane 6 when byte lanes 4 and 5 are not usable for EMIF purposes.
    • AVST-32– Byte lanes 4, 5, 6, and 7 are all effectively occupied and are not usable by the external memory interface.
Note: EMIF IP pin-out requirements for the Intel® Agilex™ 5 hard processor subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Quartus® Prime Pro Edition IP file (.qip), based on the IP configuration.