External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 130.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)

Table 131.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)

Memory WCK Frequency for this FSP

Specifies the Write Clock Frequency for this Frequency Set Point

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FQD_FREQ_MHZ)

Number of Channels in Memory Package

Number of Channels in Memory Package. This value must be consistent with the same MEM_NUM_CHANNELS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_CHANNELS)

Number of Ranks Per Channel

Number of Ranks Per Channel in Memory Package. This value must be consistent with the same MEM_NUM_RANKS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_RANKS_PER_CHANNEL)

Number of Individual DRAM Components Per Rank

Number of Individual DRAM Components Per Rank in Memory Package. This value must be consistent with the same MEM_COMPS_PER_RANK parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_COMPS_PER_RANK)

Density of Each Memory Die

Specifies the density of the memory die in Gb

(Identifier: LPDDR5_MEM_DEVICE_DENSITY_GBITS)

Enable Write Data Bus Inversion

Enables Write Data Bus Inversion

(Identifier: LPDDR5_MEM_DEVICE_WR_DBI_EN)

Enable Data Mask

Enables Data Masking for write operations

(Identifier: LPDDR5_MEM_DEVICE_DM_EN)

Table 132.  Group: Memory Interface Parameters / Data Bus
Display Name Description
DQ Width per DRAM Component

Specifies the DQ width of each LPDDR5 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP5 interfaces, select 2 components per rank at the EMIF IP level.

(Identifier: LPDDR5_MEM_DEVICE_DQ_WIDTH)

Total DQ Width Per Channel

Total DQ Width Per Channel. For LPDDR5 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank.

(Identifier: LPDDR5_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL)

Burst Length

Burst Length

(Identifier: LPDDR5_MEM_DEVICE_BURST_LENGTH)

Table 133.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Row Address Width

Specifies the row address width of this LPDDR5 DRAM component. This value is auto-derived from the specified component density.

(Identifier: LPDDR5_MEM_DEVICE_ROW_ADDR_WIDTH)

Device Maximum Bank Address Width

Specifies the maximum bank address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BA_WIDTH)

Device Maximum Bank Group Address Width

Specifies the maximum bank group address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BG_WIDTH)

Device Column Address Width

Specifies the column address width of this LPDDR5 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_COL_ADDR_WIDTH)

Device Burst Address Width

Specifies the burst address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_BURST_ADDR_WIDTH)

Table 134.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Speedbin

Maximum Data Rate for which this memory device is rated for

(Identifier: LPDDR5_MEM_DEVICE_SPEEDBIN)

Memory Write Latency Set

Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency.

(Identifier: LPDDR5_MEM_DEVICE_WLS)

Memory Read Latency

Read Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CL_CYC_FQD)

Memory Write Latency

Write Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CWL_CYC_FQD)

Table 135.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Read Postamble Mode

RDQS Postamble Mode for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_RDQS_PST_MODE_FQD)

Read Preamble Cycles

RDQS Preamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_PREAMBLE_CYC)

Read Postamble Cycles

RDQS Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_POSTAMBLE_CYC)

Write Postamble Cycles

WCK Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_WR_POSTAMBLE_CYC)

Table 136.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
Min Number of Refs Reqd

Minimum Number of Refreshes Required

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_MINNUMREFSREQ)

tRCD

RAS-to-CAS Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRCD_NS)

tRPab

All-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPAB_NS)

tRPpb

Per-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPPB_NS)

tRAS

Row Active Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_NS)

tRAS_Max

Maximum Row Active Time in us

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_MAX_US)

tWR

Write Recovery Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWR_NS)

tRRD_L

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_L_NS)

tRRD_S

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_S_NS)

tFAW

Four-bank ACTIVE window time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TFAW_NS)

tRBTP

Read Burst End to Precharge Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRBTP_NS)

tWTR_S

Write-to-Read Delay (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_S_NS)

tWTR_L

Write-to-Read Delay (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_L_NS)

tPPD

Precharge-to-Precharge Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPPD_NS)

tRC

Activate-to-Activate command period (same bank) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRC_NS)

tZQLAT

ZQCAL Latch Quiet Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQLAT_NS)

tPW_RESET

Min RESET_n low time for Reset Initialization with Stable Power Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPW_RESET_NS)

tERQE

Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQE_NS)

tERQX

Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQX_NS)

tRDQE_OD

ODT-disable from Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQE_OD_NS)

tRDQX_OD

ODT-enable from Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQX_OD_NS)

tRDQSTFE

Read/Write-based RDQS_t Training Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFE_NS)

tRDQSTFX

Read/Write-based RDQS_t Training Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFX_NS)

tCCDMW

CAS-to-CAS Delay for Masked Write in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCCDMW_NS)

tREFW

Refresh Window in ms

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFW_MS)

tREFI

Refresh Interval Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFI_NS)

tRFCab

All-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCAB_NS)

tRFCpb

Per-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCPB_NS)

tpbR2pbR

Per-Bank Refresh to Per-Bank Refresh minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2PBR_NS)

tpbR2ACT

Per-Bank Refresh to Activate minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2ACT_NS)

tCKCSH

Valid Clock Requirement before CS goes High (Power-Down AC Timings) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCKCSH_NS)

tCMDPD

Delay from valid command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCMDPD_NS)

tXP

Exit Power-Down to next valid command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXP_NS)

tCSH

Minimum CS High Pulse Width at Power Down Exit in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSH_NS)

tCSLCK

Valid Clock Requirement after Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSLCK_NS)

tCSPD

Delay time from Power Down Entry to CS going High in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSPD_NS)

tMRWPD

Delay from MRW Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRWPD_NS)

tZQPD

Delay from ZQ Calibration Start/Latch Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQPD_NS)

tESPD

Delay time from Self-Refresh Entry command to Power Down Entry command in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TESPD_NS)

tSR

Minimum Self-Refresh Time (Entry to Exit) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TSR_NS)

tXSR

Exit Self-Refresh time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXSR_NS)

tMRR

Mode Register Read Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRR_NS)

tMRW

Mode Register Write Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRW_NS)

tMRD

Mode Register Set Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRD_NS)

tOSCO

Delay time from Stop WCK2DQI/WCK2DQO Interval Oscillator Command to Mode Register Readout time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TOSCO_NS)

tDQSCK_MAX

Maximum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MAX_PS)

tDQSCK_MIN

Minimum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MIN_PS)