External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 9. Agilex™ 5 FPGA EMIF IP – Timing Closure 10. Agilex™ 5 FPGA EMIF IP – Controller Optimization 11. Agilex™ 5 FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Pin Placement 3.2.3.2. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. oct for EMIF
4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. oct for EMIF
4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axil for EMIF
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 5 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. Specific Pin Connection Requirements 6.2.3.5. Command and Address Signals 6.2.3.6. Clock Signals 6.2.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 7.3. LPDDR4 Layout Design Guidelines
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 x
7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions
7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. LPDDR4 Component Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines 7.2.3.2. Specific Pin Connection Requirements 7.2.3.3. Command and Address Signals 7.2.3.4. Clock Signals 7.2.3.5. Address and Command Pin Placement for LPDDR4 7.2.3.6. Pin Placements for Agilex™ 5 FPGA EMIF IP for LPDDR4 7.2.3.7. Pin Swapping Guidelines
7.3. LPDDR4 Layout Design Guidelines x
7.3.1. LPDDR4 PCB Stackup and Design Considerations 7.3.2. LPDDR4 General Design Considerations 7.3.3. LPDDR4 Interface Design Guidelines
7.3.3. LPDDR4 Interface Design Guidelines x
7.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 7.3.3.2. LPDDR4 Simulation Strategy
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Layout Design Guidelines
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Layout Design Guidelines x
8.3.1. LPDDR5 PCB Stackup and Design Considerations 8.3.2. LPDDR5 General Design Considerations 8.3.3. LPDDR5 Interface Design Guidelines
8.3.3. LPDDR5 Interface Design Guidelines x
8.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 8.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 8.3.3.3. LPDDR5 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Agilex™ 5 FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Hardware Debugging Guidelines 11.8. Create a Simplified Design that Demonstrates the Same Issue 11.9. Measure Power Distribution Network 11.10. Measure Signal Integrity and Setup and Hold Margin 11.11. Vary Voltage 11.12. Operate at a Lower Speed 11.13. Determine Whether the Issue Exists in Previous Versions of Software 11.14. Determine Whether the Issue Exists in the Current Version of Software 11.15. Try A Different PCB 11.16. Try Other Configurations 11.17. Debugging Checklist 11.18. Categorizing Hardware Issues 11.19. Signal Integrity Issues 11.20. Characteristics of Signal Integrity Issues 11.21. Evaluating Signal Integrity Issues 11.22. Skew 11.23. Crosstalk 11.24. Power System 11.25. Clock Signals 11.26. Address and Command Signals 11.27. Read Data Valid Window and Eye Diagram 11.28. Write Data Valid Window and Eye Diagram 11.29. Hardware and Calibration Issues 11.30. Memory Timing Parameter Evaluation 11.31. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
9. Agilex™ 5 FPGA EMIF IP – Timing Closure
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization
11. Agilex™ 5 FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 130.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 131.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Memory WCK Frequency for this FSP

Specifies the Write Clock Frequency for this Frequency Set Point

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FQD_FREQ_MHZ)
Number of Channels in Memory Package

Number of Channels in Memory Package. This value must be consistent with the same MEM_NUM_CHANNELS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_CHANNELS)
Number of Ranks Per Channel

Number of Ranks Per Channel in Memory Package. This value must be consistent with the same MEM_NUM_RANKS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_RANKS_PER_CHANNEL)
Number of Individual DRAM Components Per Rank

Number of Individual DRAM Components Per Rank in Memory Package. This value must be consistent with the same MEM_COMPS_PER_RANK parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_COMPS_PER_RANK)
Density of Each Memory Die

Specifies the density of the memory die in Gb

(Identifier: LPDDR5_MEM_DEVICE_DENSITY_GBITS)
Enable Write Data Bus Inversion

Enables Write Data Bus Inversion

(Identifier: LPDDR5_MEM_DEVICE_WR_DBI_EN)
Enable Data Mask

Enables Data Masking for write operations

(Identifier: LPDDR5_MEM_DEVICE_DM_EN)
Table 132.  Group: Memory Interface Parameters / Data Bus
Display Name Description
DQ Width per DRAM Component

Specifies the DQ width of each LPDDR5 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP5 interfaces, select 2 components per rank at the EMIF IP level.

(Identifier: LPDDR5_MEM_DEVICE_DQ_WIDTH)
Total DQ Width Per Channel

Total DQ Width Per Channel. For LPDDR5 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank.

(Identifier: LPDDR5_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL)
Burst Length

Burst Length

(Identifier: LPDDR5_MEM_DEVICE_BURST_LENGTH)
Table 133.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Row Address Width

Specifies the row address width of this LPDDR5 DRAM component. This value is auto-derived from the specified component density.

(Identifier: LPDDR5_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Maximum Bank Address Width

Specifies the maximum bank address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BA_WIDTH)
Device Maximum Bank Group Address Width

Specifies the maximum bank group address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BG_WIDTH)
Device Column Address Width

Specifies the column address width of this LPDDR5 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_COL_ADDR_WIDTH)
Device Burst Address Width

Specifies the burst address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_BURST_ADDR_WIDTH)
Table 134.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Speedbin

Maximum Data Rate for which this memory device is rated for

(Identifier: LPDDR5_MEM_DEVICE_SPEEDBIN)
Memory Write Latency Set

Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency.

(Identifier: LPDDR5_MEM_DEVICE_WLS)
Memory Read Latency

Read Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CL_CYC_FQD)
Memory Write Latency

Write Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CWL_CYC_FQD)
Table 135.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Read Postamble Mode

RDQS Postamble Mode for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_RDQS_PST_MODE_FQD)
Read Preamble Cycles

RDQS Preamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_PREAMBLE_CYC)
Read Postamble Cycles

RDQS Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_POSTAMBLE_CYC)
Write Postamble Cycles

WCK Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_WR_POSTAMBLE_CYC)
Table 136.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
Min Number of Refs Reqd

Minimum Number of Refreshes Required

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_MINNUMREFSREQ)
tRCD

RAS-to-CAS Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRCD_NS)
tRPab

All-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPAB_NS)
tRPpb

Per-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPPB_NS)
tRAS

Row Active Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_NS)
tRAS_Max

Maximum Row Active Time in us

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_MAX_US)
tWR

Write Recovery Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWR_NS)
tRRD_L

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_L_NS)
tRRD_S

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_S_NS)
tFAW

Four-bank ACTIVE window time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TFAW_NS)
tRBTP

Read Burst End to Precharge Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRBTP_NS)
tWTR_S

Write-to-Read Delay (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_S_NS)
tWTR_L

Write-to-Read Delay (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_L_NS)
tPPD

Precharge-to-Precharge Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPPD_NS)
tRC

Activate-to-Activate command period (same bank) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRC_NS)
tZQLAT

ZQCAL Latch Quiet Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQLAT_NS)
tPW_RESET

Min RESET_n low time for Reset Initialization with Stable Power Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPW_RESET_NS)
tERQE

Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQE_NS)
tERQX

Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQX_NS)
tRDQE_OD

ODT-disable from Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQE_OD_NS)
tRDQX_OD

ODT-enable from Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQX_OD_NS)
tRDQSTFE

Read/Write-based RDQS_t Training Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFE_NS)
tRDQSTFX

Read/Write-based RDQS_t Training Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFX_NS)
tCCDMW

CAS-to-CAS Delay for Masked Write in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCCDMW_NS)
tREFW

Refresh Window in ms

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFW_MS)
tREFI

Refresh Interval Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFI_NS)
tRFCab

All-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCAB_NS)
tRFCpb

Per-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCPB_NS)
tpbR2pbR

Per-Bank Refresh to Per-Bank Refresh minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2PBR_NS)
tpbR2ACT

Per-Bank Refresh to Activate minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2ACT_NS)
tCKCSH

Valid Clock Requirement before CS goes High (Power-Down AC Timings) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCKCSH_NS)
tCMDPD

Delay from valid command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCMDPD_NS)
tXP

Exit Power-Down to next valid command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXP_NS)
tCSH

Minimum CS High Pulse Width at Power Down Exit in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSH_NS)
tCSLCK

Valid Clock Requirement after Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSLCK_NS)
tCSPD

Delay time from Power Down Entry to CS going High in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSPD_NS)
tMRWPD

Delay from MRW Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRWPD_NS)
tZQPD

Delay from ZQ Calibration Start/Latch Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQPD_NS)
tESPD

Delay time from Self-Refresh Entry command to Power Down Entry command in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TESPD_NS)
tSR

Minimum Self-Refresh Time (Entry to Exit) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TSR_NS)
tXSR

Exit Self-Refresh time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXSR_NS)
tMRR

Mode Register Read Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRR_NS)
tMRW

Mode Register Write Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRW_NS)
tMRD

Mode Register Set Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRD_NS)
tOSCO

Delay time from Stop WCK2DQI/WCK2DQO Interval Oscillator Command to Mode Register Readout time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TOSCO_NS)
tDQSCK_MAX

Maximum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MAX_PS)
tDQSCK_MIN

Minimum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MIN_PS)
Level Two Title