External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 9. Agilex™ 5 FPGA EMIF IP – Timing Closure 10. Agilex™ 5 FPGA EMIF IP – Controller Optimization 11. Agilex™ 5 FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Pin Placement 3.2.3.2. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. oct for EMIF
4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. oct for EMIF
4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axil for EMIF
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 5 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. Specific Pin Connection Requirements 6.2.3.5. Command and Address Signals 6.2.3.6. Clock Signals 6.2.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 7.3. LPDDR4 Layout Design Guidelines
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 x
7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions
7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. LPDDR4 Component Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines 7.2.3.2. Specific Pin Connection Requirements 7.2.3.3. Command and Address Signals 7.2.3.4. Clock Signals 7.2.3.5. Address and Command Pin Placement for LPDDR4 7.2.3.6. Pin Placements for Agilex™ 5 FPGA EMIF IP for LPDDR4 7.2.3.7. Pin Swapping Guidelines
7.3. LPDDR4 Layout Design Guidelines x
7.3.1. LPDDR4 PCB Stackup and Design Considerations 7.3.2. LPDDR4 General Design Considerations 7.3.3. LPDDR4 Interface Design Guidelines
7.3.3. LPDDR4 Interface Design Guidelines x
7.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 7.3.3.2. LPDDR4 Simulation Strategy
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Layout Design Guidelines
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Layout Design Guidelines x
8.3.1. LPDDR5 PCB Stackup and Design Considerations 8.3.2. LPDDR5 General Design Considerations 8.3.3. LPDDR5 Interface Design Guidelines
8.3.3. LPDDR5 Interface Design Guidelines x
8.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 8.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 8.3.3.3. LPDDR5 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Agilex™ 5 FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Hardware Debugging Guidelines 11.8. Create a Simplified Design that Demonstrates the Same Issue 11.9. Measure Power Distribution Network 11.10. Measure Signal Integrity and Setup and Hold Margin 11.11. Vary Voltage 11.12. Operate at a Lower Speed 11.13. Determine Whether the Issue Exists in Previous Versions of Software 11.14. Determine Whether the Issue Exists in the Current Version of Software 11.15. Try A Different PCB 11.16. Try Other Configurations 11.17. Debugging Checklist 11.18. Categorizing Hardware Issues 11.19. Signal Integrity Issues 11.20. Characteristics of Signal Integrity Issues 11.21. Evaluating Signal Integrity Issues 11.22. Skew 11.23. Crosstalk 11.24. Power System 11.25. Clock Signals 11.26. Address and Command Signals 11.27. Read Data Valid Window and Eye Diagram 11.28. Write Data Valid Window and Eye Diagram 11.29. Hardware and Calibration Issues 11.30. Memory Timing Parameter Evaluation 11.31. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
9. Agilex™ 5 FPGA EMIF IP – Timing Closure
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization
11. Agilex™ 5 FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

6.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 67.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 68.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Number of Ranks per DIMM

Number of ranks per DIMM

Note: This parameter can be auto-computed.

(Identifier: MEM_RANKS_PER_DIMM)
DRAM Component Package Type

Specifies the packaging type of each memory component used in the interface.

(Identifier: DDR4_MEM_DEVICE_PACKAGE)
Density of Each Memory Die

Specifies the density of each memory die on the device in Gb.

(Identifier: DDR4_MEM_DEVICE_DIE_DENSITY_GBITS)
Chip ID Width

Specifies the number of chip ID pins. Only applicable to LRDIMMs or RDIMMs that use 3DS memory devices.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_CHIP_ID_WIDTH)
Density of Each Memory Component

Specifies the density of each memory component in Gb.

(Identifier: DDR4_MEM_DEVICE_COMPONENT_DENSITY_GBITS)
Enable Read DBI

Specifies whether read DBI is enabled. Read DBI is only supported on DDR4 discrete components with x8 or x16 DQ width.

(Identifier: DDR4_MEM_DEVICE_READ_DBI_EN)
Write DBI and Data Mask

Specify the write DBI and data mask setting. Neither write DBI nor data mask is supported on DDR4 components with x4 DQ width.

(Identifier: DDR4_MEM_DEVICE_DM_WRITE_DBI)
Enable Address-Command Parity

Specifies whether address-command parity is enabled. If enabled then command latency is increased by the value of parameter "Address-Command Latency Mode".

(Identifier: DDR4_MEM_DEVICE_AC_PARITY_EN)
Table 69.  Group: Memory Interface Parameters / Data Bus
Display Name Description
Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)
Device Die DQ Width

The data width of each DDR4 SDRAM die.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_DIE_DQ_WIDTH)
DQ Pins per Component

Specifies the total number of DQ pins per memory component. Must be either 4, 8, or 16.

(Identifier: DDR4_MEM_DEVICE_COMPONENT_DQ_WIDTH)
Burst Length

Specifies burst length of the device in transfers.

(Identifier: DDR4_MEM_DEVICE_BURST_LENGTH)
Table 70.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Bank Group Width

Specifies the number of bank group pins. Automatically derived from the number of data pins per component.

(Identifier: DDR4_MEM_DEVICE_BANK_GROUP_ADDR_WIDTH)
Device Bank Address Width

Specifies the number of bank address pins. Automatically set to 2.

(Identifier: DDR4_MEM_DEVICE_BANK_ADDR_WIDTH)
Device Row Address Width

Specifies the number of row address pins. Automatically derived from the device density and the number of data pins per component.

(Identifier: DDR4_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Column Address Width

Specifies the number of column address pins. Automatically set to 10.

(Identifier: DDR4_MEM_DEVICE_COL_ADDR_WIDTH)
Number of Differential Memory Clock Pairs

Specifies the number of CK_t/CK_c clock pairs exposed by the memory interface. Usually more than one pair is required for RDIMM/LRDIMM formats. The value of this parameter depends on the memory device selected. Please refer to the datasheet for your memory device.

(Identifier: DDR4_MEM_DEVICE_CK_WIDTH)
Table 71.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Clock Frequency

Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)
Memory Speed Bin

Specifies the memory speed bin using the bin names defined in JEDEC Standard No. 79-4D Chapter 10.

(Identifier: DDR4_MEM_DEVICE_SPEEDBIN)
Memory Read Latency

Specifies the read latency of the memory interface in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_CL_CYC)
Memory Write Latency

Specifies the write latency of the memory interface in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_CWL_CYC)
Address-Command Latency Mode

Specifies whether address-command latency is supported, and if enabled, the latency in cycles.

(Identifier: DDR4_MEM_DEVICE_AC_PARITY_LATENCY_MODE)
Table 72.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
tREFI

Specifies the average refresh interval in microseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TREFI_US)
tRAS

Specifies the activation-to-precharge command period in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRAS_NS)
tRCD

Specifies the activation to internal read or write delay interval in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRCD_NS)
tRP

Specifies the precharge command period in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRP_NS)
tRC

Specifies the activate-to-activate or activate-to-refresh command period in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRC_NS)
tCCD_L

Specifies the CAS-to-CAS command delay for the same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCCD_L_CYC)
tCCD_S

Specifies the CAS-to-CAS command delay for different bank groups in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCCD_S_CYC)
tRRD_L

Specifies the activation-to-activation command delay for the same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRRD_L_CYC)
tRRD_S

Specifies the activation-to-activation command delay for different bank groups in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRRD_S_CYC)
tFAW

Specifies the four-activate-window in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TFAW_NS)
tWTR_L

Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for the same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TWTR_L_CYC)
tWTR_S

Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for different bank groups in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TWTR_S_CYC)
tRTP

Specifies the internal read to precharge command delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRTP_CYC)
tWR

Specifies the write recovery time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TWR_NS)
tMRD

Specifies the mode-register command cycle time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TMRD_CYC)
tCKSRE

Specifies the number of required valid clock cycles after self-refresh entry or power-down entry.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCKSRE_CYC)
tCKSRX

Specifies the number of required valid clock cycles before self-refresh exit, power-down exit, or reset exit.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCKSRX_CYC)
tCKE

Specifies the minimum CKE pulse width in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCKE_CYC)
tCKESR

Specifies the minimum CKE low pulse width from self-refresh entry to self-refresh exit in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCKESR_CYC)
tMPRR

Specifies the multi-purpose register recovery time measured in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TMPRR_CYC)
tRFC

Specifies the refresh-to-activate or refresh-to-refresh command period.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRFC_NS)
tDIVW

Specifies the data pin receiving timing window in UI.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDIVW_TOTAL_UI)
tDQSCK

Specifies the minimum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in picoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDQSCK_PS)
tDQSQ

Specifies the latest valid transition of the associated DQ pins for a READ. tDQSQ specifically refers to the DQS_t/DQS_c to DQ skew. It is the length of time between the DQS_t/DQS_c crossing to the last valid transition of the slowest DQ pin in the DQ group associated with that DQS strobe.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDQSQ_UI)
tDQSS

Specifies the skew between the memory clock (CK) and the output data strobes used for writes in cycles. It is the time between the rising data strobe edge (DQS_t/DQS_c).

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDQSS_CYC)
tDSH

Specifies the write DQS hold time. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDSH_CYC)
tDSS

Describes the time between the falling edge of DQS to the rising edge of the next CK transition.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDSS_CYC)
tDWVp

Specifies the data valid window per device per pin measured in terms of UI.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TDVWP_UI)
tIH (Base) DC Level

Refers to the voltage level which the address/command signal must not cross during the hold window in mV. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TIH_DC_MV)
tIH (Base)

Refers to the hold time for the Address/Command bus after the rising edge of CK in picoseconds. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user chooses the "tIH (base) AC level").

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TIH_PS)
tIS (Base) AC Level

Refers to the voltage level which the address/command signal must cross and remain above during the setup margin window in mV. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TIS_AC_MV)
tIS (Base)

Refers to the setup time for the Address/Command/Control bus to the rising edge of CK in picoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TIS_PS)
tQH

Specifies the output hold time for the DQ in relation to DQS_t/DQS_c in UI. It is the length of time between the DQS_t/DQS_c pair crossing to the earliest invalid transition of the fastest DQ pin in the DQ group associated with that DQS strobe.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TQH_UI)
tQSH

Specifies the write DQS hold time in cycles. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TQSH_CYC)
tWLH

Describes the write leveling hold time in cycles. It is measured from the rising edge of DQS to the rising edge of CK.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TWLH_CYC)
tWLS

Describes the write leveling setup time. It is measured from the rising edge of CK to the rising edge of DQS.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TWLS_CYC)
tDiVW_total

Describes the minimum horizontal width of the DQ eye opening required by the receiver (memory device/DIMM). It is measured in UI.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_VDIVW_TOTAL_MV)
tRFC_DLR

Specifies the refresh cycle time across different logical rank in nanoseconds. Only applicable to 3DS devices.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRFC_DLR_NS)
tRRD_DLR

Specifies the activation-to-activation time across different logical rank in nanoseconds. Only applicable to 3DS devices.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TRRD_DLR_CYC)
tFAW_DLR

Specifies the four-activate-window across different logical ranks in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TFAW_DLR_NS)
tCCD_DLR

Specifies the CAS-to-CAS delay across different logical ranks in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCCD_DLR_NS)
tXP

Specifies the delay from power down exit with DLL on to any valid command, or from precharge power down with with DLL frozen to commands not requiring a locked DLL. Measured in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TXP_CYC)
tXS

Specifies the delay from self refresh exit to commands not requiring a locked DLL in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TXS_NS)
tXSDLL

Specifies the delay from self refresh exit to commands requiring a locked DLL in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TXS_DLL_CYC)
tCPDED

Specifies the command pass disable delay measured in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TCPDED_CYC)
tMOD

Specifies the mode register set command update delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TMOD_CYC)
tZQCS

Specifies the normal operation short calibration time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TZQCS_CYC)
tZQINIT

Specifies the power-up and reset calibration time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TZQINIT_CYC)
tZQOPER

Specifies the normal operation full calibration time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR4_MEM_DEVICE_TZQOPER_CYC)
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