External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component

The interfaces in the Agilex™ 5 EMIF IP each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types.

Table 49.  Interfaces for EMIF Calibration Inner Component
Interface Name Interface Type Description
s0_axi4lite_clk clock Axilite clock interface
s0_axi4lite_rst_n reset Axilite reset interface
s0_axi4lite axi4lite Fabric (i.e. NOC-bypass) axilite interface to the IOSSM, including the EMIF mailbox and the calbus bridge