External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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Document Table of Contents

7.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface)

LPDDR4 memory down supports single-rank configuration up to 32 bits. There are four DRAM interface signal groupings, namely: data group, command-address group, control group, and clock group. The connection between the FPGA and DRAM device uses point-to-point topology as depicted in the following two figures.

The following figure illustrates the stripline routing for inner pins.

Figure 41. Stripline Routing for Data, CA, CTRL and Clock Signals Point-to-Point Topology

The following figure illustrates the microstrip routing for the edge pins per byte.

Figure 42. Microstrip Routing for Data Signals Point-to-Point Topology

The following figure shows the connection topology for CA, CLK, CTRL signals for LPDDR4 topology in daisy-chain and T-Line connections.

Figure 43. Stripline Routing for CA, CLK, CTRL Daisy-chain and T-Line Topology

The following tables provide a comprehensive routing guideline for each of the LPDDR4 signals based on memory down topology. For example, the trace impedance, the total trace length, the maximum length of the main trace routing can be derived by subtracting break-out and break-in trace segment length routed from total trace length.

Table 109.  Stripline Routing Guide for LPDDR4 Memory Down Topology

The above table shows the stripline routing guideline for LPDDR4 memory down topology. The h value in the table represents the minimum substrate height from signal layer to reference layer. The signal trace width, and minimum spacing/gaps (in mils) between edge to edge of signal traces are based on the default stackup; however, PCB designers can use the target impedance for any other stackups.

The table below shows microstrip routing for LPDDR4 memory down topology.

Table 110.  Microstrip Routing Guide for LPDDR4 Memory Down Topology

Reset signal routing design also follows the CMD/ADD/CTRL routing design. Keep the space at least 5xh between the Reset signal to other signals on the same layer (measured edge to edge). There is no requirement to have skew matching between Reset signal and CLK signal.

Skew matching for LPDDR4 interfaces consists of both package routing skew and PCB physical routing skew. You must maintain skew matching of CA and CTRL with respect to the clock signals to ensure signals at the receiver are correctly sampled. In addition, there are skew matching requirement for DQ and DQS within a byte group, DQS and CLK. The table below provides a detailed skew matching guideline to facilitate PCB trace routing efforts. In this table, the length matching criteria represents a default PCB on an Intel platform board design; you must always follow the skew matching criteria in any other stackup.

Table 111.  Skew Matching Requirement for LPDDR4 Memory Down Topology

LPDDR4 eye margin is sensitive to crosstalk, especially when the signals are routed on deep layers in stackup. The deep-layer vertical transition induces more vertical coupling between signals and hence more crosstalk.

The maximum data rate of LPDDR4 depends on the DDR memory down configuration and the type of PCB stackup. Reduced data transfer rate is seen whenever 2 x rank LPDDR4 memory down configuration is used.