External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.3.2. DDR4 Data Width Mapping

Agilex™ 5 devices do not support flexible data lanes placement. Only fixed byte lanes within the HSIO bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an HSIO bank.
Table 74.  DDR4 Data Width Mapping
Controller Address/Command Scheme Data Width Usage BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Primary Scheme 2 DDR4 x16 GPIO 2 GPIO 2 GPIO 2 DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3 GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3a GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x16 + ECC GPIO 2 GPIO 2 DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3 GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3a GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x32 GPIO 2 DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 DQ[3] DQ[2] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a DQ[3] DQ[2] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x32 + ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
Primary + Secondary Scheme 2 DDR4 x40 1 sDQ[0] wDQ[3] wDQ[2] wDQ[1] AC2 AC1 AC0 wDQ[0]
Note:
  1. This configuration is not supported on E-Series devices. DDR4 x40 is not available in the current version of the Quartus® Prime software. DDR4 x40 requires both controllers within an I/O bank in a lockstep configuration, and AXI user data.
  2. GPIO – available for GPIO/PHYLite.
  3. DQ[ECC] – DQ/DQS group used as ECC.
  4. ES0 silicon supports address/command pin placement for DDR4 on the bottom sub-bank (BL0-BL3) only.