External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

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4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4

The interfaces in the Agilex™ 5 EMIF IP each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types.
Table 23.  Interfaces for EMIF Architecture Component
Interface Name Interface Type Description
ref_clk clock PLL reference clock input
core_init_n reset An input to indicate that core configuration is complete
usr_async_clk clock User clock interface
usr_clk clock User clock interface
usr_rst_n reset User clock domain reset interface
s0_axi4 axi4 Fabric (i.e. NOC-bypass) interface to controller
mem conduit Interface between FPGA and external memory
oct conduit On-Chip Termination (OCT) interface