External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations

This section describes PDN design guidelines for the memory side in discrete topology.

The total number of decoupling capacitors is based on single channel; if multiple channels are sharing the same power rail, the number of decoupling capacitors at memories for all channels should be scaled accordingly. You should use smaller decoupling capacitors in memory PDN design to minimize area, inductance, and resistance on the PDN path.

The following table shows the required quantity and value of decoupling capacitors on the PCB, specifically for memory side.

Table 82.  PDN Design Guidelines for the Memory Side in Discrete Topology
Memory Configuration Power Domain Decoupling Location Quantity x Value (size)
Device-down 1 Rank x 8 VDDQ/VDD shorted 4 near each x8 DRAM device 36 x 1 uF (0402)
Distribute around DRAM devices 9 x 10 uF (0603)
VPP 2 near each x8 DRAM device 18 x 1 uF (0402)
Distribute around DRAM devices 5 x 10 uF (0603)
VTT Place near Rtt (termination resistors) 16 x 1 uF (0402)
Place near Rtt (termination resistors) 4 x 10 uF (0603)
Device-down 1 Rank x 16 VDDQ/VDD shorted 4 near each x16 DRAM device 18 x 1 uF (0402)
Distribute around DRAM devices 5 x 10 uF (0603)
VPP 2 near each x16 DRAM device 10 x 1 uF (0402)
Distribute around DRAM devices 3 x 10 uF (0603)
VTT Place near Rtt (termination resistors) 8 x 1 uF (0402)
Place near Rtt (termination resistors) 2 x 10 uF (0603)