F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2. F-Tile Low Latency 100G Ethernet Design Example Description

The F-Tile Low Latency 100G Ethernet design example demonstrates the functions of the F-Tile Low Latency 100G Ethernet Intel® FPGA IP with transceiver interface compliant with the IEEE 802.3ba standard CAUI-4 specification.