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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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2. F-Tile Low Latency 100G Ethernet Design Example Description
The F-Tile Low Latency 100G Ethernet design example demonstrates the functions of the F-Tile Low Latency 100G Ethernet Intel® FPGA IP with transceiver interface compliant with the IEEE 802.3ba standard CAUI-4 specification.