Visible to Intel only — GUID: ocs1708502250339
Ixiasoft
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
Visible to Intel only — GUID: ocs1708502250339
Ixiasoft
1.6. Compiling and Configuring the Design Example in Hardware
The F-Tile Low Latency 100G Ethernet Intel® FPGA IP parameter editor allows you to compile and configure the design example on a target development kit.
- Launch the Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
- After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Agilex™ 7 device:
- Select Tools > Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Agilex™ 7 device to your Quartus® Prime Pro Edition session.
- Ensure that Mode is set to JTAG.
- Select the Intel device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Turn on Program/Configure option for the .sof.
- Click Start.