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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Quartus® Prime Pro Edition software
- QuestaSim* , VCS* , VCS* MX, Xcelium* , and Riviera-PRO* simulators
- For hardware testing:
- Agilex™ 7 I-Series Transceiver-SoC Development Kit (4x F-Tile)