Visible to Intel only — GUID: pfp1709019683657
Ixiasoft
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
Visible to Intel only — GUID: pfp1709019683657
Ixiasoft
2.4.1. Testbench
The design example simulation testbench includes a device under test (DUT), System PLL and Ethernet packet generator and monitor as shown in the figure below.
Figure 7. Block Diagram of F-Tile Low Latency 100G Ethernet Ethernet Design Example Simulation Testbench
Component | Description |
---|---|
Device under test (DUT) | The F-Tile Low Latency 100G Ethernet Intel® FPGA IP. |
Ethernet Packet Generator and Packet Monitor |
|
F-Tile Reference and System PLL Clocks Intel® FPGA IP | Generates transceiver and system PLL reference clocks. |