F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.4.1. Testbench

The design example simulation testbench includes a device under test (DUT), System PLL and Ethernet packet generator and monitor as shown in the figure below.

Figure 7. Block Diagram of F-Tile Low Latency 100G Ethernet Ethernet Design Example Simulation Testbench
Table 5.  Testbench Components
Component Description
Device under test (DUT) The F-Tile Low Latency 100G Ethernet Intel® FPGA IP.
Ethernet Packet Generator and Packet Monitor
  • Packet generator generates frames and transmit to the DUT.
  • Packet monitor monitors TX and RX datapaths and displays the frames in the simulator console.
F-Tile Reference and System PLL Clocks Intel® FPGA IP Generates transceiver and system PLL reference clocks.