F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.3. Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
Figure 6.  F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Block Diagram