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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.3. Command Line IP Generation Flow
- Run the following command:
qsys-edit --new-component-type=alt_e100_f --family=Agilex7 -- part=<part_name> --new-quartus-project=<project_name>
For example:
qsys-edit --new-component-type=alt_e100_f --family="Agilex7" --part=AGIB027R31B1E1V alt_e100_f.ip &
- In the pop-up GUI, select New Quartus Project option to create new project (.qpf) with alt_e100_f.ip included.
- Select Create.
Figure 5. F-Tile Low Latency 100G Ethernet Intel® FPGA IP GUI After Command Line Instructions