F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.4.2. Simulation Design Example Components

The testbench sends traffic through the IP, exercising the transmit side and receive side of the IP.

The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref of 156.25 MHz to the PHY. It includes a task to send and receive 10 packets.

Table 6.  Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The QuestaSim* script to run the testbench.

run_vcs.sh

The VCS* script to run the testbench.

run_vcsmx.sh

The VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

run_xcelium.sh The Xcelium* script to run the testbench.
run_riviera.do The Riviera-PRO* script to run the testbench.