F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.1. Features

  • Supports transmit (TX) cyclic redundancy check (CRC) insertion and media access controller (MAC) flow control
  • Supports preamble pass-through and link training
  • Supports Reed Solomon forward error correction (RS-FEC) feature
  • Supports MAC TX and receive (RX) statistics counters features
  • Provides testbench and simulation script
  • Supports internal serial loopback and external serial loopback
  • Provides hardware TCL script for hardware testing