Visible to Intel only — GUID: mdo1708311676443
Ixiasoft
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
Visible to Intel only — GUID: mdo1708311676443
Ixiasoft
2.1. Features
- Supports transmit (TX) cyclic redundancy check (CRC) insertion and media access controller (MAC) flow control
- Supports preamble pass-through and link training
- Supports Reed Solomon forward error correction (RS-FEC) feature
- Supports MAC TX and receive (RX) statistics counters features
- Provides testbench and simulation script
- Supports internal serial loopback and external serial loopback
- Provides hardware TCL script for hardware testing