F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.8. Design Example Interface Signals

The F-Tile Low Latency 100G Ethernet testbench is self-contained and does not require you to drive any input signals.

Table 8.  Hardware Design Example Interface Signals
Signal Direction Comments
clk100 Input

Drive at 100 MHz.

The intent is to drive this input from a 100 MHz oscillator on the board.

clk_ref Input

Drive at 156.625 MHz (default), 312.5 MHz, and 322.265625 MHz.

tx_serial[3:0] Output Transceiver PHY output serial data.
rx_serial[3:0] Input Transceiver PHY input serial data.
qsfp_rstn Output Drive to 1'b0.
qsfp_lowpwr Output Drive to 1'b1.