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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.4. Generating Tile Files
The Support-Logic generation is a pre-synthesis step used to generate tile-related files required for simulation and hardware design. The tile generation is required for all F-Tile-based design simulations. You must complete this step before the simulation.
- At the command prompt, navigate to the compilation_test_design folder in your example design as follows:
cd <your_design_path>/compilation_test_design
- Run the following command:
quartus_tlg alt_e100_f