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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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Ixiasoft
2.3.1. Design Components
Component | Description |
---|---|
F-Tile Low Latency 100G Ethernet Intel® FPGA IP | The F-Tile Low Latency 100G Ethernet Intel® FPGA IP with the following configuration:
|
F-Tile Reference and System PLL Clocks Intel® FPGA IP | F-Tile Reference and System PLL Clocks Intel® FPGA IP generates transceiver and system PLL reference clocks. |
Client Logic for Ethernet Packet Generator and Packet Monitor |
Consists of:
|
In-System Sources & Probes Intel® FPGA IP | Source and probe signals, including system reset input signal. |