F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

2.8. Design Example Interface Signals

The F-Tile Low Latency 100G Ethernet testbench is self-contained and does not require you to drive any input signals.

Table 8.  Hardware Design Example Interface Signals
Signal Direction Comments
clk100 Input

Drive at 100 MHz.

The intent is to drive this input from a 100 MHz oscillator on the board.
clk_ref Input

Drive at 156.625 MHz (default), 312.5 MHz, and 322.265625 MHz.
tx_serial[3:0] Output Transceiver PHY output serial data.
rx_serial[3:0] Input Transceiver PHY input serial data.
qsfp_rstn Output Drive to 1'b0.
qsfp_lowpwr Output Drive to 1'b1.
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