F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

2.4.3. Test Case

The simulation test case run displays output confirming the following behavior:

  1. Waiting for RX clock to settle.
  2. Printing PHY status.
  3. Sending 10 packets.
  4. Receiving 10 packets.
  5. Displaying "Testbench complete.".

The following sample output illustrates a successful simulation test run:

#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet 1...
#**Sending Packet 2...
#**Sending Packet 3...
#**Sending Packet 4...
#**Sending Packet 5...
#**Sending Packet 6...
#**Sending Packet 7...
#**Received Packet 1...
#**Sending Packet 8...
#**Received Packet 2...
#**Sending Packet 9...
#**Received Packet 3...
#**Sending Packet 10...
#**Received Packet 4...
#**Received Packet 5...
#**Received Packet 6...
#**Received Packet 7...
#**Received Packet 8...
#**Received Packet 9...
#**Received Packet 10...
#**
#** Testbench complete.
#**
#*****************************************
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