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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.7. Testing the Design Example in Hardware
After you compile the F-Tile Low Latency 100G Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.
To turn on the System Console and test the hardware design example, follow these steps:
- In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
- In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.