F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 815243
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

1.2. Generating the Design Example

Generate the design example from the IP Parameter Editor.
Figure 3. Procedure
Figure 4. Example Design Tab in the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

  1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device family and device.
  2. In the IP Catalog, locate and select F-Tile Low Latency 100G Ethernet Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP variation. Refer to the Design Components table for information about specific IP core parameters.
  6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
  7. Under Target Development Kit select the Agilex 7 Transceiver Signal Integrity Development Kit (Production).
    Note: The development kit that you select overwrites the device selection in step 1.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed (alt_e100_f_0_example_design ), browse to the new path and type the new design example directory name (<design_example_dir>).
  10. Click OK.

Section Content
Design Example Parameters

Level Two Title