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1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.2.1. Release Information for FIFO Intel® FPGA IP
4.2.2. Configuration Methods
4.2.3. Specifications
4.2.4. FIFO Functional Timing Requirements
4.2.5. SCFIFO ALMOST_EMPTY Functional Timing
4.2.6. FIFO Output Status Flag and Latency
4.2.7. FIFO Metastability Protection and Related Options
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.9. SCFIFO and DCFIFO Show-Ahead Mode
4.2.10. Different Input and Output Width
4.2.11. DCFIFO Timing Constraint Setting
4.2.12. Coding Example for Manual Instantiation
4.2.13. Instantiation Template
4.2.14. Design Example
4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.16. Guidelines for Embedded Memory ECC Feature
4.2.17. FIFO Intel® FPGA IP Parameters
4.2.18. Reset Scheme
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.3.5. Shift Register Ports and Parameters Setting
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1.1. Agilex™ 5 Embedded Memory Features
The Agilex™ 5 FPGAs offer two main types of embedded memory blocks for designers to create custom memory solutions:
- M20K Blocks:
- Capacity: 20-kilobit (Kb)
- Description: Dedicated memory resources providing a large number of independent ports (up to 4 independent ports). Ideal for larger memory arrays with high performance requirements.
- Benefits:
- High performance for data access.
- Suitable for large memory designs.
- Multiple independent ports for parallel access.
- Memory Logic Array Blocks (MLABs)
- Capacity: 640-bit
- Description: Memory blocks configured from dual-purpose Logic Array Blocks (LABs). Offers flexibility for various memory designs, especially wide and shallow arrays. Well-suited for implementing functionalities such as:
- Shift registers (commonly used in Digital Signal Processing)
- Wide and shallow FIFO buffers (First-In-First-Out)
- Filter delay lines
- Benefits:
- Flexibility for customized memory design.
- Efficient for wide, shallow memory structures.
- Can be configured as shift registers, FIFOs, or delay lines.
- In Agilex™ 5 devices, you can configure each ALM in the MLAB as ten (32×2 bits) blocks. The Agilex™ 5 devices provide one 32×20 bits simple dual-port SRAM block per MLAB.
The Agilex™ 5 FPGAs offers a diverse range of memory access options with their embedded memory blocks:
- Single-port: This mode provides a single access point for both reading and writing data. Only one operation (read or write) can occur at a time.
- Simple dual-port: This mode provides simultaneous read and write access. It offers two independent ports but with a limitation: reading and writing to the same location at the same time is restricted.
- Emulated true dual-port: This mode provides two independent ports that can perform simultaneous read and write operations on separate memory locations. It leverages FPGA fabric resources to emulate true dual-port behavior, potentially with slight performance or resource usage trade-offs compared to dedicated hardware true dual-port.
- Simple quad-port: This mode provides four access points for enhanced data throughput. Similar to simple dual-port, simultaneous access to the same location for reading and writing can lead to data corruption.
- ROM (Read-only memory): This mode provides read operations from the memory block only. Agilex™ 5 provides two options:
- Single-port: Offers a single access point for reading data.
- Dual-port: Offers simultaneous read operations from two independent ports.
Features | M20K | MLAB | |
---|---|---|---|
Maximum operating frequency |
|
850 MHz |
|
Total RAM bits (including parity bits) | 20,480 bits | 640 bits | |
Byte enable | Supported | Supported | |
Address Hold | Supported (only in simple dual-port RAM mode) | Supported for read address only. | |
Memory Initialization File (.mif) | Supported | Supported | |
Power-up state | Output ports are cleared |
|
|
Asynchronous/Synchronous Clears |
|
Output registers only.
Note: The actual data stored in the memory remains unchanged.
|
|
Same-port read-during-write |
|
Output ports set to Don't Care
Note: When designing with Agilex™ 5, you can treat the unused ports as Don't Care during simulation. However, these ports have definite values in real hardware.
|
|
Mixed-port read-during-write |
|
Output ports set to New Data, Old Data, or Don't Care
Note: When designing with Agilex™ 5, you can treat the unused ports as Don't Care during simulation. However, these ports have definite values in real hardware.
|
|
Error Correction Code (ECC) support |
|
N/A | |
Force-to-Zero | Supported | N/A | |
Coherent read memory | Supported | N/A | |
Freeze logic | Supported | N/A | |
True dual port (TDP) dual clock emulator | Supported | N/A | |
Simple dual-port mixed width | Supported | N/A | |
FIFO buffer mixed width | Supported | N/A | |
Dual-clock mode | Supported (only in simple dual-port RAM mode) | Supported | |
Full synchronous memory | Supported | Supported | |
Asynchronous memory | N/A | Only for flow-through read memory operations | |
Write/read operation triggering | Rising clock edges | Rising clock edges |
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