4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
Parameter | Legal Values | Description |
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Parameter Settings: General | ||
How will you be using the dual port RAM? | Operation mode:
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Specifies how you use the dual port RAM. |
How do you want to specify the memory size? | Type:
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Determines whether to specify the memory size in words or bits. |
Parameter Settings: Widths/Blk Type | ||
How many words of memory? | — | Specifies the number of words. |
Use different data widths on different ports | On/Off | Specifies whether to use different data widths on different ports. |
When you select With one read port and one write port or With two read/write ports, the following options are available:
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— | Specifies the width of the input and output ports. |
Ram block type |
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Specifies the memory block type. The types of memory block that are available for selection depends on your target device. |
Set the maximum block depth to |
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Specifies the maximum block depth in words. |
How should the memory be implemented? |
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Specifies the logic cell implementation method.
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Parameter Settings: Clks/Rd, Byte En | ||
Which clocking method do you want to use? |
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Specifies the clocking method to use.
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When you select With two read/write ports and Customize clocks for A and B ports clocking method, the following option is available: Emulate TDP dual clock mode |
On/Off | Specifies whether to emulate a TDP dual clock mode. The clock connection to Port A must be a slow clock and the clock connection to Port B must be a fast clock. |
When you select With one read port and one write port, the following option is available: Create a ‘rden’ read enable signal |
On/Off | Specifies whether to create a read enable signal for port B. |
When you select With two read/write ports, the following option is available: Create a ‘rden_a’ and ‘rden_b’ read enable signals |
Specifies whether to create a read enable signal for port A and B. | |
Create byte enable for port A | On/Off | Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. The option to create a byte enable for port B is only available when you select the With two read/write ports option. |
Create byte enable for port B | On/Off | |
What is the width of a byte for byte enables? |
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Specifies the width of a byte for byte enables. This option is only available when you select the Create byte enable for port A and/or Create byte enable for port B option(s). |
Enable Error Correction Check (ECC) | On/Off | Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and triple adjacent bit errors at the output of the memory. |
Enable ECC Pipeline Registers | On/Off | Specifies whether to enable the ECC Pipeline Registers before the output decoder to achieve that same performance as non-ECC mode at the expense of one cycle of latency. |
Enable ECC Encoder Bypass | On/Off | Specifies whether to enable the ECC encoder bypass feature that allows you to selectively insert parity bits into the memory through eccencparity port. |
Enable Coherent Read | On/Off | Specifies whether to enable the coherent read feature to present with coherent memory read. This feature allows you to read out current memory content, perform operation on top of the content, and write back to the same location in the same cycle. |
Parameter Settings: Regs/Clkens/Aclrs/Sclrs | ||
Which ports should be registered? When you select With one read port and one write port, the following options are available:
When you select With two read/write ports, the following options are available:
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On/Off | Specifies whether to register the read or write input and output ports. |
Clock Enables When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
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On/Off | Specifies whether to create clock enables for read and write registers. |
Addressstalls When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following option is available:
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On/Off | Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers. |
Aclr Options When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
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On/Off | Specifies whether to create an asynchronous clear port for the registered ports. Specifies whether the ‘rdaddress‘, ‘q_a’ and ‘q_b’ ports are cleared by the aclr port. |
Sclr Options When you select With one read port and one write port, the following option is available:
When you select With two read/write ports, the following options are available:
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On/Off | Specifies whether to create a synchronous clear port for the registered ports. Specifies whether the ‘rdaddress‘, ‘q_a’, and ‘q_b’ ports are cleared by the sclr port. |
Parameter Settings: Mixed Port Read-During-Write | ||
How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port? |
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Specifies the output behavior when read-during-write occurs.
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Parameter Settings: Same Port Read-During-Write (This tab is only available when you select With two read/write ports) | ||
What should the ‘q_a’ output be when reading from a memory location being written to? |
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Specifies the output behavior when read-during-write occurs.
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What should the ‘q_b’ output be when reading from a memory location being written to? | ||
Get x’s for write masked bytes instead of old data when byte enable is used | On/Off | Turn on this option to obtain ‘X’ on the masked byte. |
Parameter Settings: Mem Init | ||
Do you want to specify the initial content of the memory? |
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Specifies the initial content of the memory. To initialize the memory to zero, select No, leave it blank. To use a memory initialization file (.mif) or a hexadecimal (Altera-format) file (.hex), select Yes, use this file for the memory content data. |
Initialize memory content data to XX..X on power-up in simulation | On/Off | — |
The initial content file should conform to which port's dimensions? |
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If you select to use the initial content file for memory content data, select the port the file should conform to. |
Implement clock-enable circuitry for use in a partial reconfiguration region | On/Off | Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region. Implement clock-enable circuitry for use in a partial reconfiguration region |
Parameter Settings: Performance Optimization | ||
Enable Force to Zero | On/Off | Specifies whether to set the output to zero when you deassert the read enable signal. Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block. |
Which timing/power optimization option do you want to use? |
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Specifies the timing or power optimization option to use. This option is only applicable when you select M20K memory type on Agilex™ 5 devices. |