Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 9/03/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Configuration Methods 4.2.3. Specifications 4.2.4. FIFO Functional Timing Requirements 4.2.5. SCFIFO ALMOST_EMPTY Functional Timing 4.2.6. FIFO Output Status Flag and Latency 4.2.7. FIFO Metastability Protection and Related Options 4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.9. SCFIFO and DCFIFO Show-Ahead Mode 4.2.10. Different Input and Output Width 4.2.11. DCFIFO Timing Constraint Setting 4.2.12. Coding Example for Manual Instantiation 4.2.13. Instantiation Template 4.2.14. Design Example 4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.16. Guidelines for Embedded Memory ECC Feature 4.2.17. FIFO Intel® FPGA IP Parameters 4.2.18. Reset Scheme
4.2.3. Specifications x
4.2.3.1. Verilog HDL Prototype 4.2.3.2. VHDL Component Declaration 4.2.3.3. VHDL LIBRARY-USE Declaration 4.2.3.4. HDL Code from Parameterizable Macros Template 4.2.3.5. FIFO Signals 4.2.3.6. FIFO Parameter Settings
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.11. DCFIFO Timing Constraint Setting x
4.2.11.1. Embedded Timing Constraint 4.2.11.2. User Configurable Timing Constraint
4.2.11.2. User Configurable Timing Constraint x
4.2.11.2.1. SDC Commands
4.3. Shift Register (RAM-based) Intel® FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.3.5. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

4.2.14. Design Example

In this design example, the data from the ROM is required to be transferred to the RAM. Assuming the ROM and RAM are driven by non-related clocks, you can use the DCFIFO to transfer the data between the asynchronous clock domains effectively.
Figure 39. Component Blocks and Signal InteractionThis figure shows the component blocks and their signal interactions.
Note: The DCFIFO functions are with ECC feature enabled and implemented using M20K.
Note: Both the DCFIFO functions are only capable of handling asynchronous data transferring issues (metastable effects). You must have a controller to govern and monitor the data buffering process between the ROM, DCFIFO, and RAM. This design example provides you the write control logic (write_control_logic.v), and the read control logic (read_control_logic.v) which are compiled with the DCFIFO specifications that control the valid write or read request to or from the DCFIFO.
Note: This design example is validated with its functional behavior, but without timing analysis and gate-level simulation. The design coding such as the state machine for the write and read controllers may not be optimized. The intention of this design example is to show the use of the IP core, particularly on its control signal in data buffering application, rather than the design coding and verification processes.

To obtain the DCFIFO settings in this design example, refer to the parameter settings from the design file (dcfifo8x32.v).

The following sections include separate simulation waveforms to describe how the write and read control logics generate the control signal with respect to the signal received from the DCFIFO.

Note: For better understanding, refer to the signal names in the above figure when you go through the descriptions for the simulation waveforms.
Note: All signals in the following figures and tables have the following numerical format:
  • Signal values in binary format: reset, trclk, fifo_wrreq, fifo_wrfull
  • Signal values in HEX format: rom_addr, rom_out, fifo_in
Figure 40. Initial Write Operation to the DCFIFO Function
Table 45.  Initial Write Operation to the DCFIFO Function Waveform Description
State Description
IDLE

Before reaching 10 ns, the reset signal is high and causes the write controller to be in the IDLE state. In the IDLE state, the write controller drives the fifo_wrreq signal to low, and requests the data to be read from rom_addr=00. The ROM is configured to have an unregistered output, so that the rom_out signal immediately shows the data from the rom_addr signal regardless of the reset. This shortens the latency because the rom_out signal is connected directly to the fifo_in signal, which is a registered input port in the DCFIFO. In this case, the data (0000000000000000000000000000000000000000000000000000000000000001) is always stable and pending to be written into the DCFIFO when the fifo_wrreq signal is high during the WRITE state.

WRITE

The write controller transitions from the IDLE state to the WRITE state if the fifo_wrfull signal is low after the reset signal is deasserted. In the WRITE state, the write controller drives the fifo_wrreq signal to high, and requests for write operation to the DCFIFO. The data is encoded through the embedded ECC block in the DCFIFO. The rom_addr signal is unchanged (00) so the data is stable for at least one clock cycle before the DCFIFO actually writes in the data at the next rising clock edge.

INCADR

The write controller transitions from the WRITE state to the INCADR state, if the rom_addr signal has not yet increased to ff (that is, the last data from the ROM has not been read out). In the INDADR state, the write controller drives the fifo_wrreq signal to low, and increases the rom_addr signal by 1 (00 to 01).

- The same state transition continues as stated in IDLE and WRITE states, if the fifo_wrfull signal is low and the rom_addr signal not yet increased to ff.
Figure 41. Initial Read Operation from the DCFIFO Function
Table 46.  Initial Read Operation from the DCFIFO Function Waveform Description
State Description
IDLE

Before reaching 35 ns, the read controller is in the IDLE state because the fifo_rdempty signal is high even when the reset signal is low (not shown in the waveform). In the IDLE state, the ram_addr = ff to accommodate the increment of the RAM address in the INCADR state, so that the first data read is stored at ram_addr = 00 in the WRITE state.

INCADR

The read controller transitions from the IDLE state to the INCADR state, if the fifo_rdempty signal is low. In the INCADR state, the read controller drives the fifo_rdreq signal to high, and requests for read operation from the DCFIFO. The data is decoded and the eccstatus shows the status of the data as no error detected (00), single-bit error detected and corrected(10), or uncorrectable error (11). The ram_addr signal is increased by one (ff to 00), so that the read data can be written into the RAM at ram_addr = 00.

WRITE

From the INCADR state, the read controller always transition to the WRITE state at the next rising clock edge. In the WRITE state, it drives the ram_wren signal to high, and enables the data writing into the RAM at ram_addr = 00. At the same time, the read controller drives the ram_rden signal to high so that the newly written data is output at q at the next rising clock edge. Also, it increases the word_count signal to 1 to indicate the number of words successfully read from the DCFIFO.

--

The same state transition continues as stated in INCADR and WRITE states, if the fifo_rdempty signal is low.

Figure 42. Write Operation when DCFIFO is FULL
Table 47.  Write Operation when DCFIFO is FULL Waveform Description
State Description
INCADR

When the write controller is in the INCADR state, and the fifo_wrfull signal is asserted, the write controller transitions to the WAIT state in the next rising clock edge.

WAIT

In the WAIT state, the write controller holds the rom_addr signal (08) so that the respective data is written into the DCFIFO when the write controller transitions to the WRITE state.

The write controller stays in WAIT state if the fifo_wrfull signal is still high. When the fifo_wrfull is low, the write controller always transitions from the WAIT state to the WRITE state at the next rising clock edge.

WRITE

In the WRITE state, then only the write controller drives the fifo_wrreq signal to high, and requests for write operation to write the data from the previously held address (08) into the DCFIFO. It always transitions to the INCADR state in the next rising clock edge, if the rom_addr signal has not yet increased to ff.

--

The same state transition continues as stated in INCADR, WAIT, and WRITE states, if the fifo_wrfull signal is high.

Figure 43. Completion of Data Transfer from ROM to DCFIFO
Table 48.  Completion of Data Transfer from ROM to DCFIFO Waveform Description
State Description
WRITE When the write controller is in the WRITE state, and rom_addr = ff, the write controller drives the fifo_wrreq signal to high to request for last write operation to DCFIFO. The data 100 is the last data stored in the ROM to be written into the DCFIFO. In the next rising clock edge, the write controller transitions to the DONE state.
DONE In the DONE state, the write controller drives the fifo_wrreq signal to low.
-- The fifo_wrfull signal is deasserted because the read controller in the receiving domain continuously performs the read operation. However, the fifo_wrfull signal is only deasserted sometime after the read request from the receiving domain. This is due to the latency in the DCFIFO (rdreq signal to wrfull signal).
Figure 44. Completion of Data Transfer from DCFIFO to RAM

The fifo_rdempty signal is asserted to indicate that the DCFIFO is empty. The read controller drives the fifo_rdreq signal to low, and enables the write of the last data 100 at ram_addr =ff. The word_count signal is increased to 256 (in decimal) to indicate that all the 256 words of data from the ROM are successfully transferred to the RAM.

The last data written into the RAM is shown at the q output.

Note: To verify the results, compare the q outputs with the data in rom_initdata.hex file provided in the design example. Open the file in the Quartus® Prime software and select the word size as 256 bit. The q output must display the same data as in the file.
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