Visible to Intel only — GUID: vgo1459220652214
Ixiasoft
Visible to Intel only — GUID: vgo1459220652214
Ixiasoft
4.1.8. RAM and ROM Interface Signals
Signal | Direction | Required | Description |
---|---|---|---|
data_a | Input | Optional | Data input to port A of the memory. The data_a port is required for all RAM operation modes:
|
address_a | Input | Yes | Address input to port A of the memory. The address_a signal is required for all operation modes. |
address2_a | Input | Yes (for simple quad-port) |
Read address input to port A of the memory. The address2_a signal is required if the operation_mode parameter is set to QUAD_PORT. |
wren_a | Input | Optional | Write enable input for address_a port. The wren_a signal is required all RAM operation modes:
|
rden_a | Input | Optional | Read enable input for address_a port. The rden_a signal is supported depending on your selected memory mode and memory block. |
byteena_a | Input | Optional | Byte enable input to mask the data_a port so that only specific bytes, nibbles, or bits of the data are written. The byteena_a port is not supported in the following conditions:
|
addressstall_a | Input | Optional | Address latching input to hold the previous address of address_a port for provided that the addressstall_a port is high. |
q_a | Output | Yes | Data output from port A of the memory. The q_a port is required if the operation_mode parameter is set to any of the following values:
|
data_b | Input | Optional | Data input to port B of the memory. The data_b port is required if the operation_mode parameter is set to BIDIR_DUAL_PORT and QUAD_PORT . |
address_b | Input | Optional | Address input to port B of the memory. The address_b port is required if the operation_mode parameter is set to the following values:
|
address2_b | Input | Yes (for simple quad-port) |
Read address input to port B of the memory. The address2_b is required if the operation_mode parameter is set to QUAD_PORT. |
wren_b | Input | Yes | Write enable input for address_b port. The wren_b port is required if operation_mode is set to BIDIR_DUAL_PORT and QUAD_PORT . |
rden_b | Input | Optional | Read enable input for address_b port. The rden_b port is supported depending on your selected memory mode and memory block |
byteena_b | Input | Optional | Byte enable input to mask the data_b port so that only specific bytes, nibbles, or bits of the data are written. The byteena_b port is not supported in the following conditions:
|
q_b | Output | Yes | Data output from port B of the memory. The q_b port is required if the operation_mode is set to the following values:
The width of q_b port must be equal to the width of data_b port. |
clock0 | Input | Yes | The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
|
clock1 | Input | Optional | The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
|
clocken0 | Input | Optional | Clock enable input for clock0 port. |
clocken1 | Input | Optional | Clock enable input for clock1 port. |
eccstatus | Output | Optional | A bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs. The eccstatus port is supported if all the following conditions are met:
|
eccencbypass | Input | Optional | When active, this port allow user to inject parity flip bits through eccencparity ports. When inactive, parity flip bits is generated using internal ecc encoder. This port can only be used when enable_ecc_encoder_bypass is set to “TRUE”. |
eccencparity | Input | Optional | When eccencbypass is active, user can inject 8-bit parity flip through eccencparity port. This port can be used only when enable_ecc_encoder_bypass is set to “TRUE”. |
data | Input | Yes | Data input to the memory. The data port is required and the width must be equal to the width of the q port. |
wraddress | Input | Yes | Write address input to the memory. |
wren | Input | Yes | Write enable input for wraddress port. The wren port is required. |
rdaddress | Input | Yes | Read address input to the memory. |
rden | Input | Optional | Read enable input for rdaddress port. |
byteena | Input | Optional | Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. It is supported in Agilex™ 5 devices when you set the ram_block_type parameter to MLAB. |
wraddressstall | Input | Optional | Write address latching input to hold the previous write address of wraddress port for as long as the wraddressstall port is high. |
rdaddressstall | Input | Optional | Read address latching input to hold the previous read address of rdaddress port for as long as the rdaddressstall port is high. |
q | Output | Yes | Data output from the memory. |
inclock | Input | Yes | The following describes which of your memory clock must be connected to the inclock port, and port synchronization in different clocking modes:
|
outclock | Input | Yes | The following describes which of your memory clock must be connected to the outclock port, and port synchronization in different clocking modes:
|
inclocken | Input | Optional | Clock enable input for inclock port. |
outclocken | Input | Optional | Clock enable input for outclock port. |
aclr | Input | Optional | Asynchronously clear the output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding clear parameter, such as outdata_aclr_a and outdata_aclr_b. |
sclr | Input | Optional | Synchronously clear the output ports. The synchronous clear effect on the registered ports can be controlled through their corresponding parameter, such as outdata_sclr_a and outdata_sclr_b. |