Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

1.2. Agilex™ 5 Embedded Memory Block Signals

Table 2.  Agilex 5 Embedded Memory Block SignalsThis table defines the symbols and abbreviations used in the timing diagrams throughout this user guide. Refer to this table for details on each signal's behavior and role within the embedded memory operations. For a complete list of signal names and functionalities used within the Agilex™ 5 RAM and ROM intellectual property (IP) cores, refer to Interface Signals of the Agilex™ 5 RAM and ROM IPs table.
Signal Direction Description
clk Input Input clock signal for the memory block.
rdaddress Input Read address of the memory block. This signal specifies the location of data to be read.
rden Input Read enable signal. This signal controls when the memory block performs a read operation.
addressstall Input Address latching input signal. When high, it captures the current address value and stores it within the memory block for the next clock cycle.
Latched Address (Internal) N/A Address value captured and stored within the memory block during address latching (addressstall = 1).
q(synch) Output Synchronous output data signal. This signal carries data from the memory block synchronized with the system clock.
q(asynch) Output Asynchronous output data signal. This signal provides data output that is not directly synchronized with the system clock. Use with caution due to potential data uncertainty.
wren Input Write enable signal. This signal controls when the memory block performs a write operation.
wraddress Input Write address of the memory block. This signal specifies the location where data is written.
byteena Input Byte enable settings for write operations. This signal determines which bytes within the data word will be written during a write operation.
aclr Input Asynchronous clear signal. This signal asynchronously clears the output ports.
sclr Input Synchronous clear signal. This signal synchronously clears the output ports.
clk_enable Input Clock enable signal. This signal controls the overall clock gating for the memory block. The clock is disabled when low, effectively pausing the memory and significantly reducing its power consumption. Refer to Independent Clock Enables in Clocking Modes for more details.
data Input Input data to be written to the memory block.