Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

3.2. Consider the Concurrent Write Behavior

By default, concurrent writes can corrupt the memory content, leading to unpredictable data. Agilex™ 5 embedded memory blocks offer predictable write behavior even when two writes target the same memory location at the same time (concurrent writes).

Enabling Non-Corruptible Writes (Simulation): To ensure data integrity during concurrent writes, activate the "ENA_NON_CORRUPT=1" option within your simulator setup script. This enables a prioritized write mechanism.

Prioritized Writes with Time-Division Multiplexing (TDM) (Hardware): In actual hardware, TDM guarantees a specific write order:
  1. The value from Port B is written first.
  2. The value from Port A is written next. This ensures Port A's data prevails in case of contention.