Visible to Intel only — GUID: nmh1714979559781
Ixiasoft
Visible to Intel only — GUID: nmh1714979559781
Ixiasoft
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
The Quartus® Prime Pro Edition introduced new data output behavior through soft logic implementation. The logic checks on the input signals to determine when the mixed-port read-during-write operation occurs. It also checks on muxes to determine if the output data of the RAM should be taken from altera_syncram or the soft logic circuit.
When mixed-port read-during-write operation occurs, the new data output behavior is achieved through directly feeding the input data to the output port of the RAM, bypassing the altera_syncram module. Otherwise, the RAM always selects the altera_syncram output.
Since altera_syncram is a synchronous RAM, all input signals of the soft logic circuit must be registered to mimic the latency of altera_syncram. The output signals are registered only when the altera_syncram output is registered. New data behavior is applicable for TDP RAM in M20K block only.
- Dual clock
- Output data register/latch clear
- Byte enable
- Clock enable