Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

3.4. Consider Power-Up State and Memory Initialization

Consider the power-up state of the different types of memory blocks if your design logic evaluates the initial power-up values.
Table 17.  Initial Power-Up Values of Embedded Memory Blocks
Memory Type Output Registers Power-Up Value
MLAB Used Zero (cleared)
Bypassed Read memory contents*
M20K Used Zero (cleared)
Bypassed Zero (cleared)
*Refer to the .mif for the memory contents. If there is no .mif, the power-up value is Zero (cleared).

By default, Quartus® Prime software initializes embedded memory blocks in Agilex™ 5 devices to zero. This occurs during the FPGA configuration process.

You can specify the memory contents using a memory initialization file (.mif) for MLAB and M20K blocks. However, even if you use a .mif file, the embedded memory powers up with its output cleared. This means that the memory contents are initially zero regardless of the .mif file.