Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

2.2. Address Hold Support

The Agilex™ 5 embedded memory blocks support address hold. When enabled (setting the addressstall signal to 1), this feature captures and holds the previous address value until the next clock cycle. This can be useful for pipeline control, metastability avoidance, or specific asynchronous operations.
Note:
  1. Simple dual-port mode only: Address latching is only supported in simple dual-port mode. It's not available in other dual-port configurations or single-port mode.
  2. First clock cycle restriction: The addressstall signal cannot be asserted during the first clock cycle of operation after device configuration. Doing so might result in an unpredictable data output due to potential initialization issues.
  3. Dual-port considerations: When using dual-port memory blocks, each port has its own independent addressstall signal. This allows you to control address latching for each port individually.
Figure 2.  Address Hold This figure shows an address hold block diagram


Figure 3.  Address Hold During Read Cycle This figure shows the address hold behavior during read cycle.
Figure 4.  Address Hold During Write Cycle This figure shows the address hold behavior during write cycle.