Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

3.1. Consider the Memory Block Selection

The Quartus® Prime software automatically partitions user-defined memory into the embedded memory blocks based on the speed of your design and size constraints. For example, the Quartus® Prime software may spread out the memory across multiple available memory blocks to increase the performance of your design.

For the MLABs, you can implement single-port SRAM through emulation using the Quartus® Prime software. Emulation minimizes additional use of logic resources.

Because of the dual purpose architecture of the MLAB, the block has only data input registers, output registers, and write address registers. The MLABs utilizes read address registers from the ALMs.
Note: For Agilex™ 5 devices, the Resource Property Editor and the Timing Analyzer report the location of the M20K block as EC_X<number>_Y<number>_N<number>, even though the assigned location allowed is M20K_X<number>_Y<number>_N<number>. Embedded Cell (EC) is the sub-location of the M20K block.