Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks

The Agilex™ 5 embedded memory blocks offer byte enable functionality, allowing you to control which bytes of data are written during a write operation. This is useful when you only need to update specific parts of the memory location.
  • Masking Input Data: The byte enable signals act like a mask that filters the input data. Only bytes with corresponding high bits in the byte enable signal are written to the memory. Unwritten bytes retain their previous values.
  • Write Enable and Byte Enable: The write enable signal (wren) and the byte enable signal (byteena) work together to control write operations. By default, byte enable is always active (high) unless explicitly set low. This means the wren signal primarily controls writing, but byte enable allows for granular control within a write operation.
  • No Clear Port: Unlike some registers, byte enable registers do not have a dedicated clear port to reset all bits to zero. You need to write the desired byte enable pattern to modify its contents.
  • Byte Enable Signal: The least significant bit (LSBit) of the byteena signal corresponds to the LSByte of the data bus.
    • The byte enable signals are active high.
    • The specific width of the byteena signal depends on the chosen memory block configuration in the embedded memory IP parameter editor.