Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

2.7. Force-to-Zero

The Force-to-Zero feature helps improve timing when a RAM memory block selected is larger than a single memory block. This feature is applicable only for M20K blocks.

For example, if the selected RAM memory block has a memory depth of 4096 bits, the M20K block, which supports only a maximum memory depth of 2048 bits, requires two RAMs to be multiplexed together. When you enable this feature, you can replace OR gate with multiplexing circuitry at the output of the M20K block when performing address width stitching. As the MSB of address controls the read enable signal in the Force-to-Zero mode, the outputs of other memory blocks are forced to zero when the read enable signal is deasserted. This results the data output being read out from the output of the selected memory block only.

The option to turn on the Enable Force-to-Zero feature is available in the parameter editors of the RAM/ROM IPs.

Note: When the Enable Force-to-Zero feature option is enabled, the read enable signal does not retain previous values when you deassert the signal.