Visible to Intel only — GUID: vgo1439865066150
Ixiasoft
Visible to Intel only — GUID: vgo1439865066150
Ixiasoft
2.7. Force-to-Zero
For example, if the selected RAM memory block has a memory depth of 4096 bits, the M20K block, which supports only a maximum memory depth of 2048 bits, requires two RAMs to be multiplexed together. When you enable this feature, you can replace OR gate with multiplexing circuitry at the output of the M20K block when performing address width stitching. As the MSB of address controls the read enable signal in the Force-to-Zero mode, the outputs of other memory blocks are forced to zero when the read enable signal is deasserted. This results the data output being read out from the output of the selected memory block only.
The option to turn on the Enable Force-to-Zero feature is available in the parameter editors of the RAM/ROM IPs.