Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2024.09.03 24.2 Added a new topic: Read During Write Data Output and Memory Location Behaviors.
2024.08.02 24.2
  • Updated the description in the Agilex™ 5 Embedded Memory Features topic.
  • Updated Agilex 5 Embedded Memory Features table.
  • Added Agilex 5 Embedded Memory Block Signals topic.
  • Updated the description Agilex™ 5 Embedded Memory Architecture and Features topic.
  • Updated the description in the Byte Enable in Agilex™ 5 Embedded Memory Blocks topic.
  • Updated description in the Data Byte Output topic.
  • Updated signal name inclock to clk for Byte Enable Functional Waveform diagram.
  • Changed Address Clock Enable Support topic title to Address Hold Support and updated its description..
  • Updated the description in the Asynchronous Clear and Synchronous Clear.
  • Updated Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode diagram.
  • Updated Behavior When Asynchronous Clear is Used on Read Address Register in Registered and Unregistered Modes diagram.
  • Updated the description in the Memory Blocks Error Correction Code (ECC) Support topic.
  • Updated the description for the ECC Read-During-Write Behavior topic.
  • Removed ECC Block Diagram for M20K Memory and updated ECC Status Flags Truth Table for M20K table in the Error Correction Code Truth Table topic.
  • Updated Read/Write Clock Mode topic.
  • Updated Input/Output Clock Mode topic.
  • Updated Mixed-Width Port Configurations topic.
  • Updated True Dual Port Dual Clock Emulator topic.
  • Added True Dual-Port Mixed Port Read During Write New Data Emulation topic.
  • Updated Simple Dual-Port RAM with Registered Output Timing Diagram.
  • Updated Consider the Concurrent Write Behavior topic.
  • Added Read-During-Write (RDW) topic.
  • Updated Same-Port Read-During-Write Mode topic.
  • Updated Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode to add a note for the Don't Care output mode.
  • Updated Mixed-Port Read-During-Write Mode topic.
  • Updated Consider Power-Up State and Memory Initialization topic.
  • Added M20K memory type for New Data output mode in the Output Modes for RAM in Mixed-Port Read-During-Write Mode table.
  • Updated the header description for Parameter Settings: Mixed Port Read-During-Write in the RAM: 2-PORT Intel® FPGA IP Parameters table.
  • Updated description for read_during_write_mode_mixed_ports in the Parameters for altera_syncram table.
  • Updated description for addresstall_a, wraddresstall, and rdaddresstall in the Interface Signals of the Agilex 5 RAM and ROM IPs table.
  • Updated the description for sclr and aclr ports in the Input and Output Ports Description table.
  • Removed mentions of Agilex 5 in the following (editorial edits to the text only; no change in the technical information):
    • The description for wrreq port in the Input and Output Ports Description table.
    • The note in the FIFO Synchronous Clear and Asynchronous Clear Effect topic.
    • The footnote for Effects on the q output for normal output modes mode in the Asynchronous Clear in DCFIFO table.
    • The Guidelines for Embedded Memory ECC Feature topic.
    • The Reset Scheme topic.
2024.04.01 24.1 Initial release.