Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

4.2. FIFO Intel® FPGA IP

Altera provides FIFO Intel® FPGA IP through the parameterizable single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) functions.
The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains.
The specific names of the FIFO functions are as follows:
  • SCFIFO: single-clock FIFO
  • DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
  • DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output data)
Note: The term "DCFIFO" refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IPs, unless specified.