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1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.2.1. Release Information for FIFO Intel® FPGA IP
4.2.2. Configuration Methods
4.2.3. Specifications
4.2.4. FIFO Functional Timing Requirements
4.2.5. SCFIFO ALMOST_EMPTY Functional Timing
4.2.6. FIFO Output Status Flag and Latency
4.2.7. FIFO Metastability Protection and Related Options
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.9. SCFIFO and DCFIFO Show-Ahead Mode
4.2.10. Different Input and Output Width
4.2.11. DCFIFO Timing Constraint Setting
4.2.12. Coding Example for Manual Instantiation
4.2.13. Instantiation Template
4.2.14. Design Example
4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.16. Guidelines for Embedded Memory ECC Feature
4.2.17. FIFO Intel® FPGA IP Parameters
4.2.18. Reset Scheme
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.3.5. Shift Register Ports and Parameters Setting
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4.2. FIFO Intel® FPGA IP
Altera provides FIFO Intel® FPGA IP through the parameterizable single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) functions.
The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains.
The specific names of the FIFO functions are as follows:
- SCFIFO: single-clock FIFO
- DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
- DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output data)
Note: The term "DCFIFO" refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IPs, unless specified.
Section Content
Release Information for FIFO Intel FPGA IP
Configuration Methods
Specifications
FIFO Functional Timing Requirements
SCFIFO ALMOST_EMPTY Functional Timing
FIFO Output Status Flag and Latency
FIFO Metastability Protection and Related Options
FIFO Synchronous Clear and Asynchronous Clear Effect
SCFIFO and DCFIFO Show-Ahead Mode
Different Input and Output Width
DCFIFO Timing Constraint Setting
Coding Example for Manual Instantiation
Instantiation Template
Design Example
Gray-Code Counter Transfer at the Clock Domain Crossing
Guidelines for Embedded Memory ECC Feature
FIFO Intel FPGA IP Parameters
Reset Scheme