Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

2.4. Memory Blocks Error Correction Code (ECC) Support

The ECC feature enhances data integrity by detecting and correcting errors that occur at the output of the M20K memory blocks.

Currently, only M20K memory blocks offer ECC feature.

Enabling ECC in M20K memory blocks restricts the use of the following features:

  • Byte enable
  • Coherent read
  • Mixed data width

M20K memory blocks only support ECC feature when configured in the ×32-wide simple dual-port mode.

Figure 8. ECC Block Diagram for M20K Memory

M20K Blocks ECC Capabilites

Error Correction Strength: M20K block ECC performs the following error corrections within a 32-bit data word:
  • Single-error correction: ECC can detect and fix errors that flip a single bit from 0 to 1 or vice versa within the 32-bit data word.
  • Double-adjacent-error correction: ECC can correct errors where two bits are flipped in adjacent positions within the data word. For example, correcting the second and third bits from 1 to 0 in the data word 00101101 to 00100001.
  • Triple-adjacent-error correction: ECC can detect and correct errors where three bits are flipped in consecutive positions within the data word.
Error Coverage: It's important to note that ECC is not foolproof. It cannot guarantee detection or correction of all errors. It is particularly limited in handling:
  • Non-adjacent errors: ECC cannot correct non-adjacent errors, where two or more bits are flipped in separate positions within the data word. For example, an error that flips the second and fourth bits in the data word 10010011 to 10000111 cannot be rectified by ECC.
  • Multiple-bit errors: Errors involving more than three flipped bits within the data word.

Performance Impact: Enabling ECC introduces a slight performance penalty compared to using M20K blocks in non-ECC simple dual-port mode. This is because additional processing is required for error detection and correction.

Optional ECC Pipeline Registers: To mitigate the performance impact of ECC, you can optionally enable ECC pipeline registers before the output decoder. These registers add a one-cycle latency to the data output but can improve overall performance compared to the standard non-pipelined ECC mode.

ECC Status Flags: Two status flags, e (error) and ue (uncorrectable error), are provided as regular outputs from the M20K block. These flags indicate the ECC status of the data being read. Refer to ECC Status Flags Truth Table for M20K for further information on the status flags.