Visible to Intel only — GUID: fvo1720493204653
Ixiasoft
Visible to Intel only — GUID: fvo1720493204653
Ixiasoft
6.3. Implementing HVIO I/O PLL Reconfiguration
HVIO I/O PLL supports three functional reconfigurations without the need for another IP. PLL reconfiguration of the HVIO PLLs is done by directly interfacing with the HVIO PLL. The reconfiguration is based on the data bit settings in core_avl_address [8:0]. If configuration parameters are set to the illegal configuration settings, I/O PLL may lose the lock, which can lead to device reliability problems. Altera recommends that you strictly follow the guidelines as follows:
- You must ensure the configuration setting is a legal value so that the I/O PLL has a legal configuration. To ensure your configuration is legal, refer to the IOPLL IP Core Parameters - Advanced Parameters Tab table for the correct configuration settings.
- If the value to be reconfigured makes up only a part of one byte in the I/O PLL’s internal memory, you must perform a read-modify-write operation not to overwrite the remaining bits.
- After performing dynamic reconfiguration, the I/O PLL must be recalibrated. You must manually trigger the recalibration of the I/O PLL. Recalibration is not needed for clock gating and dynamic phase shift reconfiguration.