External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

9.1.1. Timing Analysis

Timing analysis of Agilex™ 7 M-Series EMIF IP is somewhat simpler than that of some earlier device families, because Agilex™ 7 M-Series devices have more hardened blocks and fewer soft logic registers to be analyzed, because most are user logic registers.

Your Agilex™ 7 M-Series EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.