External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 11/18/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.6. DDR5 Board Design Guidelines
7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
7.6. DDR5 Board Design Guidelines x
7.6.1. PCB Stack-up and Design Considerations 7.6.2. General Design Considerations 7.6.3. DDR Differential Signals Routing 7.6.4. Ground Plane and Return Path 7.6.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.6.6. DRAM Break-in Layout Guidelines 7.6.7. General Notes for EMIF Routing Guidelines Tables 7.6.8. DDR5 PCB Layout Guidelines 7.6.9. DDR5 RDIMM Power Management IC 7.6.10. DDR5 Simulation Strategy
7.6.8. DDR5 PCB Layout Guidelines x
7.6.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.6.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.6.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.6.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. PHY DFE Tap Bias Values for LPDDR5 8.3. MEM DFE Tap Bias Values for LPDDR5 8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.5. LPDDR5 Board Design Guidelines
8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.4.1.1. Estimating Pin Requirements 8.4.1.2. LPDDR5 Component Options 8.4.1.3. Maximum Number of Interfaces
8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.4.2.1. OCT 8.4.2.2. PLL
8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.4.3.1. General Guidelines - LPDDR5 8.4.3.2. Specific Pin Connection Requirements 8.4.3.3. Command and Address Signals 8.4.3.4. Clock Signals
8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.4.4.1. Address and Command Pin Placement for LPDDR5 8.4.4.2. LPDDR5 Data Width Mapping 8.4.4.3. LPDDR5 Byte Lane Swapping
8.5. LPDDR5 Board Design Guidelines x
8.5.1. PCB Stack-up and Design Considerations 8.5.2. General Design Considerations 8.5.3. DDR Differential Signals Routing 8.5.4. Ground Plane and Return Path 8.5.5. DRAM Break-in Layout Guidelines 8.5.6. General Notes for EMIF Routing Guidelines Tables 8.5.7. LPDDR5 PCB Layout Guidelines 8.5.8. LPDDR5 Simulation Strategy
8.5.7. LPDDR5 PCB Layout Guidelines x
8.5.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.5.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.5.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions 12.2. Sending a Mailbox Command
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes
12.2. Sending a Mailbox Command x
12.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 12.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 12.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.
Table 97.  Group: High-level Configuration / Memory Device
Parameter Name Description
Data DQ Width

Number of DQ pins per memory channel, used for data.

Default value is 32

Legal values are: 16, 32, 40

(Identifier: MEM_CHANNEL_DATA_DQ_WIDTH)
ECC DQ Width

Number of additional DQ pins per memory channel, used for out-of-band ECC. If bigger than 0, controller will enable out-of-band ECC. Otherwise, out-of-band ECC will be disabled.

Default value is 0

Legal values are: 0, 8

(Identifier: MEM_CHANNEL_ECC_DQ_WIDTH)
Die DQ Width

Number of DQ pins in each die that makes up the interface. For dual-die packages, this is the width of the die, not the width of full the package.

Default value is 16

Legal values are: 8, 16

(Identifier: MEM_DIE_DQ_WIDTH)
Die Density

Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package.

Default value is 8

Legal values are: 2, 4, 8, 16

(Identifier: MEM_DIE_DENSITY_GBITS)
CS Width

Specifies the total number of CS pins used by each channel.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_CHANNEL_CS_WIDTH)
Memory Speedbin

Specifies the speedbin of the memory device(s) of which the interface consists.

Default value is 3200W

Legal values are: 1600J, 1600K, 1600L, 1866L, 1866M, 1866N, 2133N, 2133P, 2133R, 2400P, 2400R, 2400T, 2400U, 2666T, 2666U, 2666V, 2666W, 2933V, 2933W, 2933Y, 2933AA, 3200W, 3200AA, 3200AC

(Identifier: MEM_SPEEDBIN)
Use AC Mirroring

Enable command-address mirroring for multi-rank DDR4 interfaces per JEDEC Standard.

Default value is false

(Identifier: MEM_AC_MIRRORING_EN)
Share CK Pins Between Ranks

Specifies whether all the ranks in the same channel should share one pair of memory interface differential clock.

Default value is false

(Identifier: MEM_RANKS_SHARE_CK_EN)
Use AC Parity

Specifies whether address-command parity is enabled. If enabled then command latency is increased by the value of parameter "Address-Command Latency Mode".

Default value is false

(Identifier: MEM_AC_PARITY_EN)
Auto-set Memory Operating Frequency

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency

Specifies the frequency at which the memory interface will run.

Legal values are: 666.667, 800, 933.333, 1066.667, 1200, 1333.333, 1466.667, 1600

(Identifier: MEM_OPERATING_FREQ_MHZ)
Table 98.  Group: High-level Configuration / PHY
Parameter Name Description
Auto-set PLL Reference Clock Frequency

if true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency.

Default value is true

(Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN)
Enable Advanced List of PLL Reference Clock Frequencies

If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length.

Default value is false

(Identifier: PHY_REFCLK_ADVANCED_SELECT_EN)
Reference Clock Frequency

Specifies the reference clock frequency for the EMIF IOPLL.

(Identifier: PHY_REFCLK_FREQ_MHZ)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan.

Default value is BOT

Legal values are: BOT, TOP

(Identifier: PHY_AC_PLACEMENT)
Alert_n AC-Lane Index

Specifies the AC lane index in which to place the ALERT_N pin.

Default value is AC2

Legal values are: AC2, AC3

(Identifier: PHY_ALERT_N_PLACEMENT)
Force Using 4 AC Lanes

Specifies if the minimum number of AC lanes for the memory interface should be forced to 4.

Default value is false

(Identifier: PHY_FORCE_MIN_4_AC_LANES_EN)
Auto-set Mainband Access Mode

if true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN)
Mainband Access Mode

Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller.

Legal values are: NOC, ASYNC, SYNC

(Identifier: PHY_MAINBAND_ACCESS_MODE)
Auto-set Sideband Access Mode

if true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN)
Sideband Access Mode

Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM.

Legal values are: NOC, FABRIC

(Identifier: PHY_SIDEBAND_ACCESS_MODE)
Pin Swizzle Map

Specifies the swizzle map for the data lanes and pins.

(Identifier: PHY_SWIZZLE_MAP)
Use Debug Toolkit

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

Default value is false

(Identifier: DEBUG_TOOLS_EN)
Instance ID

Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value.

Default value is 0

Legal values are: from 0 to 6

(Identifier: INSTANCE_ID)
Table 99.  Group: High-level Configuration / Controller
Parameter Name Description
Use ECC Autocorrection

If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported.

Default value is true

(Identifier: CTRL_ECC_AUTOCORRECT_EN)
Use Data Masking

Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled.

Default value is false

(Identifier: CTRL_DM_EN)
Use WDBI

Specifies whether write Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_WR_DBI_EN)
Use RDBI

Specifies whether read Data-bus-inversion is enabled by the controller.

Default value is false

(Identifier: CTRL_RD_DBI_EN)
Table 100.  Group: Advanced: Memory Timing / Overrides / JEDEC_TABLE
Parameter Name Description
JEDEC Parameter

Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: MEM_WR_PREAMBLE_MODE, MEM_RD_PREAMBLE_MODE, MEM_CL_CYC, MEM_CWL_CYC, MEM_TREFI_NS, MEM_TRAS_NS, MEM_TRCD_NS, MEM_TRP_NS, MEM_TRC_NS, MEM_TCCD_L_NS, MEM_TCCD_S_NS, MEM_TRRD_L_NS, MEM_TRRD_S_NS, MEM_TFAW_NS, MEM_TWTR_L_NS, MEM_TWTR_S_NS, MEM_TWR_NS, MEM_TMRD_NS, MEM_TCKSRE_NS, MEM_TCKSRX_NS, MEM_TCKE_NS, MEM_TCKESR_CYC, MEM_TMPRR_NS, MEM_TRFC_NS, MEM_TDQSCK_NS, MEM_TDQSS_CYC, MEM_TDSH_NS, MEM_TDSS_NS, MEM_TIH_NS, MEM_TIS_NS, MEM_TQSH_NS, MEM_TWLH_NS, MEM_TWLS_NS, MEM_TRFC_DLR_NS, MEM_TRRD_DLR_NS, MEM_TFAW_DLR_NS, MEM_TCCD_DLR_NS, MEM_TXP_NS, MEM_TXS_NS, MEM_TXS_DLL_NS, MEM_TCPDED_NS, MEM_TMOD_NS, MEM_TZQCS_NS, MEM_TZQINIT_CYC, MEM_TZQOPER_CYC

(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME)
Table 101.  Group: Advanced: Memory Timing / Values
Parameter Name Description
Write Preamble Length

Specifies the write preamble length in cycles.

(Identifier: MEM_WR_PREAMBLE_MODE)
Read Preamble Length

Specifies the read preamble length in cycles.

(Identifier: MEM_RD_PREAMBLE_MODE)
Read Latency

Read Latency of the memory device in clock cycles.

(Identifier: MEM_CL_CYC)
Write Latency

Write Latency in clock cycles.

(Identifier: MEM_CWL_CYC)
tREFI

Specifies the average refresh interval in nanoseconds.

(Identifier: MEM_TREFI_NS)
tRAS

Specifies the activation-to-precharge command period in nanoseconds.

(Identifier: MEM_TRAS_NS)
tRCD

Specifies the activation to interval read or write delay interval in nanoseconds.

(Identifier: MEM_TRCD_NS)
tRP

Specifies the precharge command period in nanoseconds.

(Identifier: MEM_TRP_NS)
tRC

Specifies the activate-to-activate or activate-to-refresh command period in nanoseconds.

(Identifier: MEM_TRC_NS)
tCCD_L

Specifies the CAS-to-CAS command delay for the same bank group in nanoseconds.

(Identifier: MEM_TCCD_L_NS)
tCCD_S

Specifies the CAS-to-CAS command delay for different bank groups in nanoseconds.

(Identifier: MEM_TCCD_S_NS)
tRRD_L

Specifies the activation-to-activation command delay for the same bank group in nanoseconds.

(Identifier: MEM_TRRD_L_NS)
tRRD_S

Specifies the activation-to-activation command delay for different bank groups in nanoseconds.

(Identifier: MEM_TRRD_S_NS)
tFAW

Specifies the four-activate-window in nanoseconds.

(Identifier: MEM_TFAW_NS)
tWTR_L

Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for the same bank group in nanoseconds.

(Identifier: MEM_TWTR_L_NS)
tWTR_S

Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for different bank groups in nanoseconds.

(Identifier: MEM_TWTR_S_NS)
tWR

Specifies the write recovery time in nanoseconds.

(Identifier: MEM_TWR_NS)
tMRD

Specifies the mode-register command cycle time in nanoseconds.

(Identifier: MEM_TMRD_NS)
tCKSRE

Specifies the amount of time, in nanoseconds, required after self-refresh entry or power-down entry.

(Identifier: MEM_TCKSRE_NS)
tCKSRX

Specifies the amount of time, in nanoseconds, required before self-refresh exit, power-down exit, or reset exit.

(Identifier: MEM_TCKSRX_NS)
tCKE

Specifies the minimum CKE low pulse width from self-refresh entry to self-refresh exit in nanoseconds.

(Identifier: MEM_TCKE_NS)
tCKESR

Specifies the minimum CKE low pulse width from self-refresh entry to self-refresh exit in memory clock cycles.

(Identifier: MEM_TCKESR_CYC)
tMPRR

Specifies the multi-purpose register recovery time measured in nanoseconds.

(Identifier: MEM_TMPRR_NS)
tRFC

Specifies the refresh-to-activate or refresh-to-refresh command period in nanoseconds.

(Identifier: MEM_TRFC_NS)
tDQSCK

Specifies the minimum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in nanoseconds.

(Identifier: MEM_TDQSCK_NS)
tDQSS

Specifies the skew between the memory clock (CK) and the output data strobes used for writes in cycles. It is the time between the rising data strobe edge (DQS_t/DQS_c).

(Identifier: MEM_TDQSS_CYC)
tDSH

Specifies the write DQS hold time, in nanoseconds. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.

(Identifier: MEM_TDSH_NS)
tDSS

Describes the time, in nanoseconds, between the falling edge of DQS to the rising edge of the next CK transition.

(Identifier: MEM_TDSS_NS)
tIH (Base)

Refers to the hold time for the Address/Command bus after the rising edge of CK in nanoseconds. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user chooses the "tIH (base) AC level").

(Identifier: MEM_TIH_NS)
tIS (Base)

Refers to the setup time for the Address/Command/Control bus to the rising edge of CK in nanoseconds.

(Identifier: MEM_TIS_NS)
tQSH

Specifies the write DQS hold time in nanoseconds. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.

(Identifier: MEM_TQSH_NS)
tWLH

Describes the write leveling hold time in nanoseconds. It is measured from the rising edge of DQS to the rising edge of CK.

(Identifier: MEM_TWLH_NS)
tWLS

Describes the write leveling setup time in nanoseconds. It is measured from the rising edge of CK to the rising edge of DQS.

(Identifier: MEM_TWLS_NS)
tRFC_DLR

Specifies the refresh cycle time across different logical rank in nanoseconds. Only applicable to 3DS devices.

(Identifier: MEM_TRFC_DLR_NS)
tRRD_DLR

Specifies the activation-to-activation time across different logical rank in nanoseconds. Only applicable to 3DS devices.

(Identifier: MEM_TRRD_DLR_NS)
tFAW_DLR

Specifies the four-activate-window across different logical ranks in nanoseconds.

(Identifier: MEM_TFAW_DLR_NS)
tCCD_DLR

Specifies the CAS-to-CAS delay across different logical ranks in nanoseconds.

(Identifier: MEM_TCCD_DLR_NS)
tXP

Specifies the delay from power down exit with DLL on to any valid command, or from precharge power down with with DLL frozen to commands not requiring a locked DLL. Measured in nanoseconds.

(Identifier: MEM_TXP_NS)
tXS

Specifies the delay from self refresh exit to commands not requiring a locked DLL in nanoseconds.

(Identifier: MEM_TXS_NS)
tXSDLL

Specifies the delay from self refresh exit to commands requiring a locked DLL in nanoseconds.

(Identifier: MEM_TXS_DLL_NS)
tCPDED

Specifies the command pass disable delay measured in nanoseconds.

(Identifier: MEM_TCPDED_NS)
tMOD

Specifies the mode register set command update delay in nanoseconds.

(Identifier: MEM_TMOD_NS)
tZQCS

Specifies the normal operation short calibration time in nanoseconds.

(Identifier: MEM_TZQCS_NS)
tZQINIT

Specifies the power-up and reset calibration time in cycles.

(Identifier: MEM_TZQINIT_CYC)
tZQOPER

Specifies the normal operation full calibration time in cycles.

(Identifier: MEM_TZQOPER_CYC)
Table 102.  Group: Advanced: Analog Overrides / Overrides / ANALOG_TABLE
Parameter Name Description
Analog Parameter

Name of Analog Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: PHY_TERM_X_R_S_AC_OUTPUT_OHM, PHY_TERM_X_R_S_CK_OUTPUT_OHM, PHY_TERM_X_R_S_DQ_OUTPUT_OHM, PHY_TERM_X_DQ_SLEW_RATE, PHY_TERM_X_R_T_DQ_INPUT_OHM, PHY_TERM_X_DQ_VREF, PHY_TERM_X_R_T_REFCLK_INPUT_OHM, MEM_ODT_DQ_X_TGT_WR, MEM_ODT_DQ_X_NON_TGT_WR, MEM_ODT_DQ_X_NON_TGT_RD, MEM_ODT_DQ_X_RON, MEM_VREF_DQ_X_RANGE, MEM_VREF_DQ_X_VALUE

(Identifier: ANALOG_PARAM_DERIVATION_PARAM_NAME)
Table 103.  Group: Advanced: Analog Overrides / Values
Parameter Name Description
AC Drive Strength

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_AC_OUTPUT_OHM)
CK Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_CK_OUTPUT_OHM)
FPGA DQ Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_DQ_OUTPUT_OHM)
DQ Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

Legal values are: SLOW, MEDIUM, FAST, FASTEST

(Identifier: PHY_TERM_X_DQ_SLEW_RATE)
DQ Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_40_OHM_CAL, RT_50_OHM_CAL, RT_60_OHM_CAL

(Identifier: PHY_TERM_X_R_T_DQ_INPUT_OHM)
DQ Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

Legal values are: from 0 to 100

(Identifier: PHY_TERM_X_DQ_VREF)
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_OFF, RT_DIFF

(Identifier: PHY_TERM_X_R_T_REFCLK_INPUT_OHM)
Target Write Termination

Specifies the target termination to be used during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_TGT_WR)
Non-Target Write Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_NON_TGT_WR)
Non-Target Read Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_NON_TGT_RD)
Memory DQ Drive Strength

Specifies the termination to be used when driving read data from memory. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: 7, 5

(Identifier: MEM_ODT_DQ_X_RON)
VrefDQ Range

Specifies which of the memory protocol defined ranges will be used.

Legal values are: 1, 2

(Identifier: MEM_VREF_DQ_X_RANGE)
VrefDQ Value

Specifies the initial VrefDQ value to be used.

Legal values are: from 60.00 to 92.50, from 45.00 to 75.00

(Identifier: MEM_VREF_DQ_X_VALUE)
Table 104.  Group: Example Design / Fileset Types
Parameter Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

Default value is VERILOG

Legal values are: VERILOG, VHDL

(Identifier: EX_DESIGN_HDL_FORMAT)
Generate Synthesis Fileset

Generate Synthesis Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SYNTH)
Generate Simulation Fileset

Generate Simulation Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SIM)
Table 105.  Group: Example Design / User PLL
Parameter Name Description
Auto-set User PLL Output Clock Frequency

if true, let IP select a reference clock frequency for the user PLL in the example design; if false, let user set a custom value for this parameter.

Default value is true

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN)
User PLL Output Clock Frequency

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode).

Default value is 570

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ)
User PLL Reference Clock Frequency

PLL reference clock frequency in MHz for PLL supplying the core clock.

Default value is 100

(Identifier: EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ)
NOC Reference Clock Frequency

Reference Clock Frequency for the NOC control IP.

Default value is 100

Legal values are: 25, 100, 125

(Identifier: EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ)
Table 106.  Group: Example Design / Traffic Generator
Parameter Name Description
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled.

Default value is JTAG

Legal values are: EXPORT, JTAG

(Identifier: EX_DESIGN_TG_CSR_ACCESS_MODE)
Traffic Generator Program

Specifies the traffic pattern to be run.

Default value is MEDIUM

Legal values are: SHORT, MEDIUM, LONG, INFINITE

(Identifier: EX_DESIGN_TG_PROGRAM)
Table 107.  Group: Example Design / Performance Monitor
Parameter Name Description
Enable Performance Monitor for Channel 0

If true, example design will include a Performance Monitor instance connected to Channel 0.

Default value is false

(Identifier: EX_DESIGN_PMON_CH0_EN)
Level Two Title