External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 11/18/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.6. DDR5 Board Design Guidelines
7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
7.6. DDR5 Board Design Guidelines x
7.6.1. PCB Stack-up and Design Considerations 7.6.2. General Design Considerations 7.6.3. DDR Differential Signals Routing 7.6.4. Ground Plane and Return Path 7.6.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.6.6. DRAM Break-in Layout Guidelines 7.6.7. General Notes for EMIF Routing Guidelines Tables 7.6.8. DDR5 PCB Layout Guidelines 7.6.9. DDR5 RDIMM Power Management IC 7.6.10. DDR5 Simulation Strategy
7.6.8. DDR5 PCB Layout Guidelines x
7.6.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.6.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.6.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.6.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. PHY DFE Tap Bias Values for LPDDR5 8.3. MEM DFE Tap Bias Values for LPDDR5 8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.5. LPDDR5 Board Design Guidelines
8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.4.1.1. Estimating Pin Requirements 8.4.1.2. LPDDR5 Component Options 8.4.1.3. Maximum Number of Interfaces
8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.4.2.1. OCT 8.4.2.2. PLL
8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.4.3.1. General Guidelines - LPDDR5 8.4.3.2. Specific Pin Connection Requirements 8.4.3.3. Command and Address Signals 8.4.3.4. Clock Signals
8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.4.4.1. Address and Command Pin Placement for LPDDR5 8.4.4.2. LPDDR5 Data Width Mapping 8.4.4.3. LPDDR5 Byte Lane Swapping
8.5. LPDDR5 Board Design Guidelines x
8.5.1. PCB Stack-up and Design Considerations 8.5.2. General Design Considerations 8.5.3. DDR Differential Signals Routing 8.5.4. Ground Plane and Return Path 8.5.5. DRAM Break-in Layout Guidelines 8.5.6. General Notes for EMIF Routing Guidelines Tables 8.5.7. LPDDR5 PCB Layout Guidelines 8.5.8. LPDDR5 Simulation Strategy
8.5.7. LPDDR5 PCB Layout Guidelines x
8.5.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.5.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.5.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions 12.2. Sending a Mailbox Command
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes
12.2. Sending a Mailbox Command x
12.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 12.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 12.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

12.1.2. Mailbox Command Definitions

Table 205.  CMD_TYPE Definition
CMD_TYPE Value Description
CMD_NOP 0x00 No operation command.
CMD_GET_SYS_INFO 0x01 Retrieving information about the IO96B configuration.
CMD_GET_MEM_INFO 0x02 Retrieving information about the memory interface operation.
CMD_TRIG_CONTROLLER_OP 0x04 Triggering memory controller-related operations.
CMD_TRIG_MEM_CAL_OP 0x05 Triggering calibration events.
Table 206.  CMD_REQ Definition
Bit Name Description Access Reset
[31:29] CMD_TARGET_IP_TYPE Indicates the type of IP, as follows:
  • 0x0 – Not used.
  • 0x1 – Primary MC of primary IO96B.
  • 0x2 – Secondary MC of primary IO96B.
  • 0x3 – Primary MC of secondary IO96B.
  • 0x4 – Secondary MC of secondary IO96B.
 Read-Write 0x0
[28:24] CMD_TARGET_IP_INSTANCE_ID IP identifier. Read-Write 0x00
[23:16] CMD_TYPE The type of command that the user wants the firmware to perform. Read-Write 0x00
[15:0] CMD_OPCODE The opcode of the command that the user wants the firmware to perform. Read-Write 0x00
Table 207.  CMD_TARGET_IP_TYPE Definition
Multi-channel/Lockstep Configurations CMD_TARGET_IP_TYPE
1 – Primary MC, Primary IO96B 2 – Secondary MC, Primary IO96B 3 – Primary MC, Secondary IO96B 4 – Secondary MC, Secondary IO96B
LPDDR4/5 2CHx16 CH1 CH2    
LPDDR4/5 4CHx16 CH1 CH2 CH3 CH4
DDR5 2CHx16 CH1 CH2    
DDR5 2CHx32 CH1   CH2  
DDR5 x40 lockstep CH1 *    
DDR4 x40 lockstep CH1 *    
DDR4 x64, x72 lockstep CH1 * * *
Note: * These controllers are used but have no (or limited) mailbox features due to limited lockstep capabilities.
Table 208.  Command Definitions
CMD_REQ Description

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <UNUSED>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <UNUSED>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_SYS_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_INTF_INFO

Command to get the memory interface IP type and instance ID of all the IPs in the IO96B.

[Inputs] N/A

[Outputs ]

CMD_RESPONSE_DATA_SHORT [1:0]: NUM_USED_MEM_INTF

Number of memory interfaces instantiated.

CMD_RESPONSE_DATA_0 [31:29]: INTF_0_IP_TYPE Indicates the type of IP for Interface 0:

0x0 – Not used

0x1 – EMIF

CMD_RESPONSE_DATA_0 [28:24]: INTF_0_INSTANCE_ID IP identifier for Interface 0.

CMD_RESPONSE_DATA_1 [31:29]: INTF_1_IP_TYPE

Indicates the type of IP for Interface 1:

0x0 – Not used

0x1 – EMIF

CMD_RESPONSE_DATA_1 [28:24]: INTF_1_INSTANCE_ID

IP identifier for Interface 1.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_TECHNOLOGY

Command to get the memory technology of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [2:0]: MEM_TECHNOLOGY

Reports the memory type as below:

0x0 = DDR4, 0x1 = DDR5, 0x2 = DDR5_RDIMM, 0x3 = LPDDR4, 0x4 = LPDDR5, 0x5 = QDRIV

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEMCLK_FREQ_KHZ

Command to get the memory clock frequency of the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [1:0]: FREQUENCY_SET_POINT

Get clock frequency for the specified frequency set point.

0x0 = Frequency set point 0

0x1 = Frequency set point 1

0x2 = Frequency set point 2

CMD_PARAM_0 [2:2]: USE_CURRENT_FSP

Get clock frequency for the current frequency set point.

0x0 = Use FSP specified using FREQUENCY_SET_POINT.

0x1 = Use current FSP

[Outputs]

CMD_RESPONSE_DATA_0: DRAM_CLK_FREQ_KHZ

Reports the memory clock frequency in KHz for the input frequency set point.

[Errors]

CMD_RESPONSE_STATUS - STATUS_CMD_RESPONSE_ERROR:

000 – No errors

111 – The FSP specified using FREQUENCY_SET_POINT is not defined.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_WIDTH_INFO

Command to get the memory width information of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [7:0]: DQ_WIDTH

CMD_RESPONSE_DATA_0 [15:8]: CS_WIDTH

CMD_RESPONSE_DATA_0 [23:16]: C_WIDTH

CMD_RESPONSE_DATA_1 [7:0]: TOTAL_MEM_CAPACITY

Memory device capacity in Gb (gigabits) calculated as:

CAPACITY = (DQ_WIDTH / DEVICE_WIDTH) * DEVICE_DENSITY

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_ENABLE_SET

Command to enable different ECC modes for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [1:0]: ECC_ENABLE

Set the current ECC error reporting (single-bit and double-bit errors) and correcting (single-bit errors) that is enabled.

’b00 = ECC is disabled. Data is written to the memory without ECC values, and data is returned to the user interface without being verified for accuracy.

’b01 = ECC is enabled, but without detection or correction.

’b10 = ECC is enabled with detection, but correction is not supported. When an error is found on a read operation, ECC reporting parameters are updated for read commands. Erroneous data is returned to the user on read commands and written to the memory on write commands.

’b11 = ECC is enabled with detection and correction. When an error is found on a read operation, the ECC reporting parameters are updated for read commands. Single bit errors are corrected automatically by the controller in both read and write commands.

CMD_PARAM_0[2:2]: ECC_TYPE

‘b0 = Out-of-Band ECC

‘b1 =In-line ECC

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_ENABLE_STATUS

Command to get the ECC enable status of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [1:0]: ECC_ENABLE

Reports the current ECC error reporting (single-bit and double-bit errors) and correcting (single-bit errors) that is enabled.

’b00 = ECC is disabled. Data is written to the memory without ECC values, and data is returned to the user interface without being verified for accuracy.

’b01 = ECC is enabled, but without detection or correction.

’b10 = ECC is enabled with detection, but correction is not supported. When an error is found on a read operation, ECC reporting parameters are updated for read commands. Erroneous data is returned to the user on read commands and written to the memory on write commands.

’b11 = ECC is enabled with detection and correction. When an error is found on a read operation, the ECC reporting parameters are updated for read commands. Single bit errors are corrected automatically by the controller in both read and write commands.

CMD_RESPONSE_DATA_SHORT[2:2]:

ECC_TYPE

‘b0 = Out-of-Band ECC

‘b1 =In-line ECC

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_STATUS

Command to get status of ECC interrupts for the memory interface specified using the instance ID.

[Inputs]

[Outputs]

CMD_RESPONSE_DATA_0 [13:0]: ECC_INTERRUPT_STATUS

Reports the interrupts related to the ECC logic.

Bit [13] = A RMW Read Link ECC double-bit error has been detected.

Bit [12] = A Read Link ECC double-bit error has been detected.

Bit [11] = A Read Link ECC single-bit error has been detected.

Bit [10] = A Write Link ECC double-bit error has been detected by the periodic MRR to MR43.

Bit [9] = A Write Link ECC single-bit error has been detected by the periodic MRR to MR43.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation.

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_ACK

Command to acknowledge and clear the ECC interrupts for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [13:0]: ECC_INTERRUPT_ACK

Used to acknowledge and clear the interrupts related to the ECC logic.

Bit [13] = A RMW Read Link ECC double-bit error has been detected.

Bit [12] = A Read Link ECC double-bit error has been detected.

Bit [11] = A Read Link ECC single-bit error has been detected.

Bit [10] = A Write Link ECC double-bit error has been detected by the periodic MRR to MR43.

Bit [9] = A Write Link ECC single-bit error has been detected by the periodic MRR to MR43.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation.

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_MASK

Command to set mask for ECC interrupts for the memory interface specified using the instance ID, in order to disable specific ECC interrupts.

[Inputs]

CMD_PARAM_0 [13:0]: ECC_INTERRUPT_MASK

If any bit is set to ’b1 in this parameter, the corresponding interrupt does NOT trigger an interrupt on the top-level EMIF interrupt signal.

Bit [13] = A RMW Read Link ECC double-bit error has been detected

Bit [12] = A Read Link ECC double-bit error has been detected.

Bit [11] = A Read Link ECC single-bit error has been detected.

Bit [10] = A Write Link ECC double-bit error has been detected by the periodic MRR to MR43.

Bit [9] = A Write Link ECC single-bit error has been detected by the periodic MRR to MR43.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

[Outputs] N/A

CMD_REQ column is:

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_WRITEBACK_ENABLE

Command to set automatic writing of corrected errors on read operation for the memory interface specified using the instance ID

CMD_PARAM_0 [0:0]: ECC_WRITEBACK_EN

Enables automatic writing of corrected data on single bit correctable errors on read operations. This parameter is only relevant if ECC is enabled with detection and correction (ECC_ENABLE = ’b11). Note: No writebacks will be issued during BIST. ’b0 = Disable. ’b1 = Enable

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection and correction not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_GET_SBE_INFO

Command to get the details on the single-bit (SBE) or correctable errors detected by ECC for the memory interface specified using the instance ID. This command should be called only if all of the following conditions are true:

1. A correctable ECC event occurs.

2. ECC is enabled in the ECC_ENABLE parameter (’b01, ’b10 or ’b11).

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [31:0]: ECC_SBE_INFO_SIZE

Holds the size of the single bit error details. The value of this is 192 bits.

CMD_RESPONSE_DATA_1 [31:0]: ECC_SBE_INFO_PTR

Holds the offset pointer of the single bit error details. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [1]: ECC_SBE_ADDR [37:0]

Holds the address of the read data that caused a single-bit correctable ECC event. The Controller pads this parameter with zeros for any address bits not used by the controller. Here, the 5th bit of OFFSET [0] has the 37th bit, and the lowest bit of OFFSET [1] has the 0th bit of ECC_SBE_ADDR.

OFFSET [2] to OFFSET [3]: ECC_SBE_DATA [63:0]

Holds the pre-corrected data associated with a single-bit correctable ECC event.

OFFSET [4]: ECC_SBE_ID [6:0]

Holds the source ID associated with a single-bit correctable ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

OFFSET [5]: ECC_SBE_SYND [7:0]

Holds the syndrome value associated with a single-bit correctable ECC error event. This value indicates which bit of the check code or data was erroneous. The ECC Syndrome Codes table shows the syndrome corresponding to the single bit errors.

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_GET_DBE_INFO

Command to get the details on the double-bit (DBE) or uncorrectable errors detected by ECC for the memory interface specified using the instance ID. This command should be called only if all of the following conditions are true:

1. An uncorrectable ECC event occurs.

2. ECC is enabled in the ECC_ENABLE parameter (’b01, ’b10 or ’b11.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [31:0]: ECC_DBE_INFO_SIZE

Holds the size of the double bit error details. The value of this is 192 bits.

CMD_RESPONSE_DATA_1 [31:0]: ECC_DBE_INFO_PTR

Holds the offset pointer of the double bit error details. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [1]: ECC_DBE_ADDR [37:0]

Holds the address of the read data that caused a double-bit uncorrectable ECC event. The Controller pads this parameter with zeros for any address bits not used by the controller. Here, the 5th bit of OFFSET [0] has the 37th bit, and the lowest bit of OFFSET [1] has the 0th bit of ECC_SBE_ADDR.

OFFSET [2] to OFFSET [3]: ECC_DBE_DATA [63:0]

Holds the data associated with a double-bit uncorrectable ECC event.

OFFSET [4]: ECC_DBE_ID [6:0]

Holds the source ID associated with a double-bit uncorrectable ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

OFFSET [5]: ECC_DBE_SYND [7:0]

Holds the syndrome bits associated with a double-bit un-correctable ECC error event. This controller can indicate that only 2 bits of the data and/or check code are erroneous but can not identify which bits. The ECC Syndrome Codes table shows the syndrome corresponding to the single bit errors.

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_IN_PROGRESS_STATUS

Command to check if the ECC scrub is in-progress for the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_IN_PROGRESS

Reports the scrubbing operation status. This parameter is read-only. ’b0 = Not actively performing a scrubbing operation. ’b1 = The Controller is in the process of performing a scrubbing operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_0_START

Command to start ECC scrub in mode 0 where scrub is performed at regular intervals for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_INTERVAL

Sets the minimum interval between two ECC scrubbing commands, in number of controller clock cycles. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables interval operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0. The burst lengths for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_1_START

Command to start ECC scrub in mode 1 where scrub is performed when the controller is idle for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_IDLE_CNT

Defines the number of controller clock cycles that the scrubbing engine waits in the Controller’s idle state before starting scrubbing operations. The Controller is considered idle when the command queue is empty. When this condition is detected, an internal counter loads with the value programmed in this parameter and count down on each controller clock. When the counter expires, either the scrubbing operation begins or the next address is tested. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables idle operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0. The burst lengths for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value

programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INJECT_ERROR

Command to force a specific check code to be written into memory interface specified using the instance ID for diagnostic purposes or for flagging a particular memory address as erroneous for future accesses. The procedure is as follows:

  1. Set the ECC_ENABLE parameter to enable detection (’b1x).
  2. Ensure that no writes to the controller are pending.
  3. Send ECC_INJECT_ERROR command through mailbox setting the ECC_XOR_CHECK_BITS input parameter. Use the syndromes to program the ECC_XOR_CHECK_BITS parameter. Each byte of the ECC_XOR_CHECK_BITS parameter controls the ECC event forcing for a separate user-word space. For example, setting a value of 0xF4 as ECC_XOR_CHECK_BITS will result in the check bits to be updated and written to the memory such that it flags a single-bit correctable error on bit [0] of the user-word on subsequent access of the same address.
  4. Execute a write command for an aligned user word. The controller will XOR the ECC_XOR_CHECK_BITS parameter with the generated checksum bits from the word written to the memory. The next read command to the same address will force the ECC error.
  5. Depending on the programming of the ECC_XOR_CHECK_BITS parameter, a single bit, double bit or multi-bit ECC error will occur. For single bit and double bit errors, the appropriate bit in the ECC_INTERRUPT_STATUS parameter will be set to ’b1 and the ECC error signature parameters will be filled with the relevant information.

[Inputs]

CMD_PARAM_0 [31:0]: ECC_XOR_CHECK_BITS

The check bits generated by the next write operation will be XOR’ed with this parameter. The result will be written into memory as the new check value.

ECC_XOR_CHECK_BITS [31:24] maps to user word [255:192]

ECC_XOR_CHECK_BITS [23:16] maps to user word [191:128]

ECC_XOR_CHECK_BITS [15:8] maps to user word [127:64]

ECC_XOR_CHECK_BITS [7:0] maps to user word [63:0]

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_STANDARD_MODE_START

Command to initiate Original MOVI1 3N BIST algorithm for data checking for the memory interface specified using the instance ID. This command MUST be followed by BIST_RESULTS_STATUS to get the results of the BIST operation and resume normal operation of the memory controller. BIST operations are supported only for designs with DBI disabled.

[Inputs]

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic will check. As an example, if the addr_space parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Only used if BIST_FULL_MEM is ‘b0.

A BIST test must cover a minimum of 2 bursts. Therefore, the user must program this parameter to a value such that the start address and end address of the BIST test will encompass a minimum of 2 bursts. The burst length for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 – 16

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [36:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST initiated successfully

‘b0 – BIST initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored. For example, BIST_STANDARD_MODE_START should be followed by BIST_RESULTS_STATUS command to restored saved state and resume normal memory controller operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_RESULTS_STATUS

Command to get BIST results for the previously initiated BIST operation for memory interface specified using the instance ID. You need to resend this command every time before reading the CMD_RESPONSE_STATUS register for checking the BIST_STATUS .

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_STATUS

Holds the status of the BIST operation.

’b0 = BIST operation still in progress if previously initiated.

’b1 = BIST operation has been completed.

[Command-Specific Error]

‘b00 – No errors

‘b01 – Could not restore saved state. BIST_STANDARD_MODE_START command MUST be immediately followed by BIST_RESULTS_STATUS to get the results of the BIST operation, restore saved state, and resume normal operation of the memory controller. The populated results, if any, may be invalid.

CMD_RESPONSE_DATA_SHORT [3:3]: BIST_RESULT

Holds the result of the BIST operation. For this BIST mode, the test ends at the first failure, or completely checks the specified data range if no failures are found. This value is valid when BIST_STATUS indicates that the BIST operation has completed.

’b0 = Data check failed. ’b1 = Data check passed.

CMD_RESPONSE_DATA_0 [31:0]: BIST_FAIL_RESULT_SIZE

Holds the size of the BIST failure results. The value of this is 640 bits.

CMD_RESPONSE_DATA_1 [31:0]: BIST_FAIL_RESULT_PTR

Holds the offset pointer of the BIST failure results. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [8]: BIST_EXP_DATA [287:0]

Holds the expected read data for a BIST data check failure. Here, the highest bit of OFFSET [0] has the 287th bit, and the lowest bit of OFFSET [8] has the 0th bit of BIST_EXP_DATA.

OFFSET [9] to OFFSET [10]: BIST_FAIL_ADDR [37:0]

Holds the actual failing address for a BIST data check failure.

OFFSET [11] to OFFSET [20]: BIST_FAIL_DATA [287:0]

Holds the actual failing data for a BIST data check failure.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_MEM_INIT_START

Command to initiate memory initialization BIST for the memory interface specified using the instance ID. Memory initialization programming allows a selectable range of memory to be initialized with a programmable data value. This command MUST be followed by BIST_MEM_INIT_STATUS to get the results of the BIST memory initialization operation and resume normal operation of the memory controller.

[Inputs] N/A

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic will check. As an example, if the addr_space parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Only used if BIST_FULL_MEM is ‘b0.

Note: A BIST test must cover a minimum of 2 bursts. Therefore, the user must program this parameter to a value such that the start address and end address of the BIST test will encompass a minimum of 2 bursts. The burst length for different protocols are:

DDR4 - 8

DDR5/LPDDR4/LPDDR5 - 16

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [37:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

CMD_PARAM_3: BIST_DATA_PATTERN

Specifies the data pattern to use for the memory initialization.

‘b00 – Initialize memory to all zeros.

‘b10 – Use data pattern specified using the values set using commands BIST_SET_DATA_PATTERN_UPPER and BIST_SET_DATA_PATTERN_LOWER before issuing BIST_MEM_INITIAL_START command.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST memory initialization initiated successfully

‘b0 – BIST memory initialization initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored. For example, BIST_STANDARD_MODE_START should be followed by BIST_RESULTS_STATUS command to restored saved state and resume normal memory controller operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_MEM_INIT_STATUS

Command to get BIST memory initialization status for the previously initiated BIST operation for memory interface specified using the instance ID

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_STATUS

Holds the status of the BIST operation.

’b0 = Memory content initialization operation still in progress if previously initiated.

’b1 = Memory content initialization operation has been completed.

[Command-Specific Errors]

‘b00 – No errors

‘b01 – Could not restore saved state. BIST_MEM_INIT_START command MUST be immediately followed by BIST_MEM_INIT_STATUS to get the results of the BIST operation, restore saved state, and resume normal operation of the memory controller. The populated results, if any, may be invalid.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_UPPER

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [287:256]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [255:224]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [223:192]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [191:160]

Defines the data pattern bits [287:160] to be used. Only data corresponding to active portion of core word is used while the inactive portion is ignored.

The active portion of the core word depends on the DQ width per channel and the burst length. For example:

- DDR5/LPDDR4/LPDDR5 (BL16) will use BIST_DATA_PATTERN [255:0] for x32 and BIST_DATA_PATTERN [127:0] for x16.

- DDR4 (BL8) will use BIST_DATA_PATTERN [127:0] for x32 and BIST_DATA_PATTERN [63:0] for x16.

If the axi4_rdata bus width is greater than the width of the active BIST_DATA_PATTERN, you will get repeated BIST_DATA_PATTERN when reading from the initialized memory locations. For example:

- DDR4 x32: axi4_rdata[255:0] = { 2{BIST_DATA_PATTERN[127:0] } }

- DDR4 x16: axi4_rdata[255:0] = { 4{BIST_DATA_PATTERN[63:0] } }

[Outputs] N/A

[Command-Specific Errors]

‘b00 – No errors

‘b01 – Cannot set upper data pattern for slim interface.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_LOWER

CMD_PARAM_4 [31:0]: BIST_DATA_PATTERN [159:128]

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [127:96]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [95:64]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [63:32]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [31:0]

Defines the data pattern bits [223:0] to be used. Only data corresponding to active portion of the core word is used while inactive portion is ignored.

The active portion of the core word depends on the DQ width per channel and the burst length. For example:

- DDR5/LPDDR4/LPDDR5 (BL16) will use BIST_DATA_PATTERN [255:0] for x32 and BIST_DATA_PATTERN [127:0] for x16.

- DDR4 (BL8) will use BIST_DATA_PATTERN [127:0] for x32 and BIST_DATA_PATTERN [63:0] for x16.

If the axi4_rdata bus width is greater than the width of the active BIST_DATA_PATTERN, you will get repeated BIST_DATA_PATTERN when reading from the initialized memory locations. For example:

- DDR4 x32: axi4_rdata[255:0] = { 2{BIST_DATA_PATTERN[127:0] } }

- DDR4 x16: axi4_rdata[255:0] = { 4{BIST_DATA_PATTERN[63:0] } }

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_ENTER

Command to cause the Interface to enter a low power state. Note that other interface operations, including recalibration and mode register reads and writes, can cause automatic exits from some low-power states.

[Inputs]

CMD_PARAM_0[3:0]: LP_STATE

Specified the low power state the interface should enter:

‘b1000 – Self-Refresh Long (DDR4/DDR5 Only)

‘b1001 – Self-Refresh Long with Memory Clock Gating (DDR4/DDR5 Only)

‘b1010 – Self-Refresh Long with Memory Clock and Controller Clock Gating (DDR4/DDR5 Only)

‘b1101 – Self-Refresh Power Down Long (LPDDR4/LPDDR5 Only)

‘b1110 – Self-Refresh Power Down Long with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b1111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating (LPDDR4/LPDDR5 Only)

[Outputs] N/A

[Error Codes]

‘b000 – No errors

‘b001 – The Selected Low Power State is Not Available for the Current Protocol

‘b010 – The Selected Low Power State is invalid/Does not Exist.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_EXIT

Command to exit any low power state.

[Inputs] N/A

[Outputs] N/A

[Error Codes]

‘b000 – No errors

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_STATUS

Command to get the Current Low Power State of the Interface.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT[0:0]:

Valid Bit. The Data in CMD_RESPONSE_DATA_0[5:0] is only valid if this bit is ‘b1.

‘b0 – Invalid, the Interface is currently transitioning into or out of a low power state

‘b1 – Valid.

CMD_RESPONSE_DATA_0[5:0]: Current Interface Low Power State

‘b000000 - Idle

‘b000001 – Active Power Down

‘b000010 – Active Power Down with Memory Clock Gating

‘b000011 – Pre-Charge Power Down

‘b000100 – Pre-Charge Power Down with Memory Clock Gating

‘b000101 – Self-Refresh Short

‘b000110 – Self-Refresh Short with Memory Clock Gating

‘b001000 – Self-Refresh Long

‘b001001 – Self-Refresh Long with Memory Clock Gating

‘b001010 – Self-Refresh Long with Memory Clock and Controller Clock Gating

‘b001011 – Self-Refresh Power Down Short

‘b001100 – Self-Refresh Power Down Short with Memory Clock Gating

‘b001101 – Self-Refresh Power Down

‘b001110 – Self-Refresh Power Down Long with Memory Clock Gating

‘b001111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating

[Error Codes]

‘b000 – No errors

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = CHANGE_FSP_LP5

Command to change the FSP when using the LPDDR5 protocol.

[Inputs]

CMD_PARAM_0 [1:0]:

TARGET_FSP

‘b00 – FSP 0

‘b01 – FSP 1

‘b10 – FSP 2

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]:

FSP_CHANGE_STATUS

‘b1 – The FSP was changed successfully.

‘b0 – The FSP was not changed successfully.

[Error Codes]

‘b000 – No errors.

‘b001 – Current Protocol is not LPDDR5.

‘b010 – The current FSP is equal to the target FSP – No change is needed.

‘b011 – The FSP could not be changed.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_AUTO

Command to cause the Interface to enter certain automatic low power states. Supported low power modes for this command are listed below as valid options. Do not use LP_MODE_EXIT opcode to exit from the automatic low power states. Note that other interface operations, including recalibration and mode register reads and writes, sending read/write request to the controller can cause automatic exits from some low-power states.

[Inputs]

CMD_PARAM_0 [3:0]:

Specified the low power state the interface should enter.

‘b0000 – Disable automatic low power mode.

‘b0001 – Active Power Down (All Protocols).

‘b0010 – Active Power Down with Memory Clock Gating (LPDDR4/LPDDR5 only).

‘b0011 – Pre-Charge Power Down (All Protocols).

‘b0100 – Pre-Charge Power Down with Memory Clock Gating (LPDDR4/LPDDR5 only).

‘b0101 – Self-Refresh Short (DDR4/DDR5 only).

‘b0110 – Self-Refresh Short with Memory Clock Gating (DDR4/DDR5 only).

‘b1011 – Self-Refresh Power Down Short (LPDDR4/LPDDR5 only).

‘b1100 – Self-Refresh Power Down Short with Memory Clock Gating (LPDDR4/LPDDR5 only).

CMD_PARAM_1 [11:0]:

Defines the number of idle controller clocks that can elapse before the controller will automatically issue an entry into the low power state specified

[Outputs]

[Error Codes]

‘b000 – No errors

‘b001 – The selected low power state is invalid for the current protocol.

‘b010 – The selected low power state is invalid/does not exist.

‘b011 – The idle clock count should not be zero.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_MEM_CAL_OP

CMD_REQ [15:0]: CMD_OPCODE = TRIG_MEM_CAL

Command to trigger a memory calibration for the memory interface specified using the instance ID. You should only recalibrate the memory interface for debug purposes.

For multi-channel interfaces, recalibration can be initiated by sending the TRIG_MEM_CAL command as below:

  • 1 channel – 1 request to the interface
  • 2 channel LPDDR4/LPDDR5 – 1 request to one of the interfaces
  • 2 channel DDR5 – 2 separate requests to the interfaces in each IO96B
  • 4 channel LPDDR4/LPDDR5 – 2 requests to one of the interfaces in each IO96B

[Inputs]

[Outputs]

CMD_RESPONSE_DATA_SHORT [0]: MEM_CAL_INITIATED

‘b1 – Memory calibration triggered successfully

‘b0 – Memory calibration triggering failed

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <UNUSED>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <UNUSED>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_MEM_CAL_OP

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_CAL_STATUS

Command to get the memory calibration status for the memory interface specified using the instance ID.

[Inputs]

[Outputs]

CMD_RESPONSE_DATA_0 [2:0]: INTF_0_CAL_STATUS_PTR

Pointer to the Calibration Status of the memory interface 0. The data at pointer location OFFSET [0] is as below:

‘b001 – Calibration was successful

‘b010 – Calibration failed

‘b100 – Calibration ongoing

‘b000 – INTF_0 unused

CMD_RESPONSE_DATA_1 [2:0]: INTF_1_CAL_STATUS_PTR

Pointer to the Calibration Status of the memory interface 1. The data at pointer location OFFSET [0] is as below:

‘b001 – Calibration was successful.

‘b010 – Calibration failed.

‘b100 – Calibration ongoing.

‘b000 – INTF_1 unused.
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