External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

8.2.3.2. Specific Pin Connection Requirements

PLL

For LPDDR5, you must constrain the PLL reference clock to the address and command lanes only.

  • You must constrain differential reference clocks to pin indices 10 and 11 in lane 2 when placing command address pins in lane 3 and lane 2.
  • The sharing of PLL reference clocks across multiple LPDDR5 interfaces is permitted within an I/O bank.

OCT

For LPDDR5, you must constrain the RZQ pin to the address and command lanes only.
  • You must constrain RZQ to pin index 2 in lane 3 when placing command address pins in lane 3 and lane 2.
  • The sharing of RZQ across multiple LPDDR5 interfaces is permitted within an I/O bank.

RDQS/DQ/DM

For LPDDR5 x8 DQS grouping, the following rules apply:

  • You may use pin indices 0, 1, 2, 3, 8, 9, 10, and 11 within a lane for DQ mode pins only.
  • You must use pin index 4 for the RDQS_p pin only.
  • You must use pin index 5 for the RDQS_n pin only.
  • You must ensure that pin index 7 remains unused. Pin index 7 is not available for use as a general purpose I/O.
  • You must use pin index 6 for the DM pin only.