Visible to Intel only — GUID: ihd1685441908765
Ixiasoft
Visible to Intel only — GUID: ihd1685441908765
Ixiasoft
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
Parameter | Value | Description |
---|---|---|
Number of RX channels |
|
Specifies the number of receiver channels in the interface. Default is 1. Place the refclk pin on the same I/O bank as the receiver. |
Number of TX channels | 0 to 47 | Specifies the number of transmitter channels in the interface. |
RX functional mode |
|
Specifies the functional mode of the receiver interface. Default is RX Non-DPA. These options are not available if Number of RX channels is 0. |
Data rate |
|
Specifies the data rate (in Mbps) of a single serial channel. Default is 800.0. |
SERDES factor |
|
Select the rate of serialization and deserialization for the LVDS SERDES interface. Default is 4.
Note: Serialization factor of 8 is available only in M-Series FPGAs production devices.
|
I/O Standard |
|
Select the I/O standard of the LVDS SERDES interface. |